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[Qemu-devel] [PATCH 07/16] tcg-ppc64: Use TCGMemOp within qemu_ldst rout
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 07/16] tcg-ppc64: Use TCGMemOp within qemu_ldst routines |
Date: |
Wed, 4 Sep 2013 14:04:56 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/ppc64/tcg-target.c | 82 +++++++++++++++++++++++++++-----------------------
1 file changed, 44 insertions(+), 38 deletions(-)
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 73b7034..7da6a2f 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -807,22 +807,28 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int
opx, TCGReg rt,
}
}
-static const uint32_t qemu_ldx_opc[8] = {
-#ifdef TARGET_WORDS_BIGENDIAN
- LBZX, LHZX, LWZX, LDX,
- 0, LHAX, LWAX, LDX
-#else
- LBZX, LHBRX, LWBRX, LDBRX,
- 0, 0, 0, LDBRX,
-#endif
+static const uint32_t qemu_ldx_opc[16] = {
+ [MO_UB] = LBZX,
+ [MO_UW] = LHZX,
+ [MO_UL] = LWZX,
+ [MO_Q] = LDX,
+ [MO_SW] = LHAX,
+ [MO_SL] = LWAX,
+ [MO_BSWAP | MO_UB] = LBZX,
+ [MO_BSWAP | MO_UW] = LHBRX,
+ [MO_BSWAP | MO_UL] = LWBRX,
+ [MO_BSWAP | MO_Q] = LDBRX,
};
-static const uint32_t qemu_stx_opc[4] = {
-#ifdef TARGET_WORDS_BIGENDIAN
- STBX, STHX, STWX, STDX
-#else
- STBX, STHBRX, STWBRX, STDBRX,
-#endif
+static const uint32_t qemu_stx_opc[16] = {
+ [MO_UB] = STBX,
+ [MO_UW] = STHX,
+ [MO_UL] = STWX,
+ [MO_Q] = STDX,
+ [MO_BSWAP | MO_UB] = STBX,
+ [MO_BSWAP | MO_UW] = STHBRX,
+ [MO_BSWAP | MO_UL] = STWBRX,
+ [MO_BSWAP | MO_Q] = STDBRX,
};
static const uint32_t qemu_exts_opc[4] = {
@@ -854,7 +860,7 @@ static const void * const qemu_st_helpers[4] = {
in CR7, loads the addend of the TLB into R3, and returns the register
containing the guest address (zero-extended into R4). Clobbers R0 and R2.
*/
-static TCGReg tcg_out_tlb_read(TCGContext *s, int s_bits, TCGReg addr_reg,
+static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits, TCGReg addr_reg,
int mem_index, bool is_read)
{
int cmp_off
@@ -927,7 +933,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, int s_bits,
TCGReg addr_reg,
/* Record the context of a call to the out of line helper code for the slow
path for a load or store, so that we can later generate the correct
helper code. */
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, int opc,
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOp opc,
int data_reg, int addr_reg, int mem_index,
uint8_t *raddr, uint8_t *label_ptr)
{
@@ -951,8 +957,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld,
int opc,
static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
- int opc = lb->opc;
- int s_bits = opc & 3;
+ TCGMemOp opc = lb->opc & MO_SSIZE;
+ TCGMemOp s_bits = lb->opc & MO_SIZE;
reloc_pc14(lb->label_ptr[0], (uintptr_t)s->code_ptr);
@@ -967,7 +973,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s,
TCGLabelQemuLdst *lb)
tcg_out_call(s, (tcg_target_long)qemu_ld_helpers[s_bits], 1);
- if (opc & 4) {
+ if (opc & MO_SIGN) {
uint32_t insn = qemu_exts_opc[s_bits];
tcg_out32(s, insn | RA(lb->datalo_reg) | RS(TCG_REG_R3));
} else {
@@ -979,7 +985,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s,
TCGLabelQemuLdst *lb)
static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
- int opc = lb->opc;
+ TCGMemOp s_bits = lb->opc & MO_SIZE;
reloc_pc14(lb->label_ptr[0], (uintptr_t)s->code_ptr);
@@ -990,11 +996,11 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s,
TCGLabelQemuLdst *lb)
tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, lb->addrlo_reg);
tcg_out_rld(s, RLDICL, TCG_REG_R5, lb->datalo_reg,
- 0, 64 - (1 << (3 + opc)));
+ 0, 64 - (1 << (3 + s_bits)));
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R6, lb->mem_index);
tcg_out32(s, MFSPR | RT(TCG_REG_R7) | LR);
- tcg_out_call(s, (tcg_target_long)qemu_st_helpers[opc], 1);
+ tcg_out_call(s, (tcg_target_long)qemu_st_helpers[s_bits], 1);
tcg_out_b(s, 0, (uintptr_t)lb->raddr);
}
@@ -1015,10 +1021,11 @@ void tcg_out_tb_finalize(TCGContext *s)
}
#endif /* SOFTMMU */
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
+static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp opc)
{
TCGReg addr_reg, data_reg, rbase;
- uint32_t insn, s_bits;
+ uint32_t insn;
+ TCGMemOp s_bits = opc & MO_SIZE;
#ifdef CONFIG_SOFTMMU
int mem_index;
void *label_ptr;
@@ -1026,7 +1033,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args, int opc)
data_reg = *args++;
addr_reg = *args++;
- s_bits = opc & 3;
#ifdef CONFIG_SOFTMMU
mem_index = *args;
@@ -1055,7 +1061,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args, int opc)
} else if (insn) {
tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
} else {
- insn = qemu_ldx_opc[s_bits];
+ insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
insn = qemu_exts_opc[s_bits];
tcg_out32(s, insn | RA(data_reg) | RS(data_reg));
@@ -1067,7 +1073,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args, int opc)
#endif
}
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
+static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGMemOp opc)
{
TCGReg addr_reg, rbase, data_reg;
uint32_t insn;
@@ -1847,38 +1853,38 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args,
break;
case INDEX_op_qemu_ld8u:
- tcg_out_qemu_ld(s, args, 0);
+ tcg_out_qemu_ld(s, args, MO_UB);
break;
case INDEX_op_qemu_ld8s:
- tcg_out_qemu_ld(s, args, 0 | 4);
+ tcg_out_qemu_ld(s, args, MO_SB);
break;
case INDEX_op_qemu_ld16u:
- tcg_out_qemu_ld(s, args, 1);
+ tcg_out_qemu_ld(s, args, MO_TEUW);
break;
case INDEX_op_qemu_ld16s:
- tcg_out_qemu_ld(s, args, 1 | 4);
+ tcg_out_qemu_ld(s, args, MO_TESW);
break;
case INDEX_op_qemu_ld32:
case INDEX_op_qemu_ld32u:
- tcg_out_qemu_ld(s, args, 2);
+ tcg_out_qemu_ld(s, args, MO_TEUL);
break;
case INDEX_op_qemu_ld32s:
- tcg_out_qemu_ld(s, args, 2 | 4);
+ tcg_out_qemu_ld(s, args, MO_TESL);
break;
case INDEX_op_qemu_ld64:
- tcg_out_qemu_ld(s, args, 3);
+ tcg_out_qemu_ld(s, args, MO_TEQ);
break;
case INDEX_op_qemu_st8:
- tcg_out_qemu_st(s, args, 0);
+ tcg_out_qemu_st(s, args, MO_UB);
break;
case INDEX_op_qemu_st16:
- tcg_out_qemu_st(s, args, 1);
+ tcg_out_qemu_st(s, args, MO_TEUW);
break;
case INDEX_op_qemu_st32:
- tcg_out_qemu_st(s, args, 2);
+ tcg_out_qemu_st(s, args, MO_TEUL);
break;
case INDEX_op_qemu_st64:
- tcg_out_qemu_st(s, args, 3);
+ tcg_out_qemu_st(s, args, MO_TEQ);
break;
case INDEX_op_ext8s_i32:
--
1.8.1.4
- [Qemu-devel] [PATCH 00/16] Streamlining endian handling in TCG, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 03/16] tcg-aarch64: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 04/16] tcg-arm: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 02/16] tcg-i386: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 01/16] tcg: Add TCGMemOp, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 05/16] tcg-s390: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 06/16] tcg-ppc: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 07/16] tcg-ppc64: Use TCGMemOp within qemu_ldst routines,
Richard Henderson <=
- [Qemu-devel] [PATCH 08/16] tcg-hppa: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 09/16] tcg-mips: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 10/16] tcg-sparc: Use TCGMemOp within qemu_ldst routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 11/16] tcg: Add qemu_ld_st_i32/64, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 12/16] exec: Add both big- and little-endian memory helpers, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 14/16] tcg-i386: Remove "cb" output restriction from qemu_st8 for i386, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 13/16] tcg-i386: Tidy softmmu routines, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 15/16] tcg-i386: Support new ldst opcodes, Richard Henderson, 2013/09/04
- [Qemu-devel] [PATCH 16/16] target-ppc: Convert to new ldst opcodes, Richard Henderson, 2013/09/04