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Re: [Qemu-devel] [PATCH v5 3/3] hw/pci: partially handle pci master abor
From: |
Marcel Apfelbaum |
Subject: |
Re: [Qemu-devel] [PATCH v5 3/3] hw/pci: partially handle pci master abort |
Date: |
Mon, 16 Sep 2013 12:11:32 +0300 |
On Mon, 2013-09-16 at 12:04 +0300, Michael S. Tsirkin wrote:
> On Mon, Sep 16, 2013 at 11:21:16AM +0300, Marcel Apfelbaum wrote:
> > A MemoryRegion with negative priority was created and
> > it spans over all the pci address space.
> > It "intercepts" the accesses to unassigned pci
> > address space and will follow the pci spec:
> > 1. returns -1 on read
> > 2. does nothing on write
> >
> > Note: setting the RECEIVED MASTER ABORT bit in the STATUS register
> > of the device that initiated the transaction will be
> > implemented in another series
> >
> > Signed-off-by: Marcel Apfelbaum <address@hidden>
> > ---
> > Changes from v4:
> > - Addressed Michael S. Tsirkin comments
> > - Changed PCI master_abort_mem ops endian-nes to DEVICE_LITTLE_ENDIAN
> > - Fixed: overlap master_abort_mem at offset 0, not at
> > bus->address_space_mem.addr
> >
> > hw/pci/pci.c | 26 ++++++++++++++++++++++++++
> > include/hw/pci/pci_bus.h | 1 +
> > 2 files changed, 27 insertions(+)
> >
> > diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> > index ad1c1ca..d8a1b11 100644
> > --- a/hw/pci/pci.c
> > +++ b/hw/pci/pci.c
> > @@ -283,6 +283,24 @@ const char *pci_root_bus_path(PCIDevice *dev)
> > return rootbus->qbus.name;
> > }
> >
> > +static uint64_t master_abort_mem_read(void *opaque, hwaddr addr, unsigned
> > size)
> > +{
> > + return -1ULL;
> > +}
> > +
> > +static void master_abort_mem_write(void *opaque, hwaddr addr, uint64_t val,
> > + unsigned size)
> > +{
> > +}
> > +
> > +static const MemoryRegionOps master_abort_mem_ops = {
> > + .read = master_abort_mem_read,
> > + .write = master_abort_mem_write,
> > + .endianness = DEVICE_LITTLE_ENDIAN,
> > +};
> > +
> > +#define MASTER_ABORT_MEM_PRIORITY INT_MIN
> > +
> > static void pci_bus_init(PCIBus *bus, DeviceState *parent,
> > const char *name,
> > MemoryRegion *address_space_mem,
> > @@ -294,6 +312,14 @@ static void pci_bus_init(PCIBus *bus, DeviceState
> > *parent,
> > bus->address_space_mem = address_space_mem;
> > bus->address_space_io = address_space_io;
> >
> > +
> > + memory_region_init_io(&bus->master_abort_mem, OBJECT(bus),
> > + &master_abort_mem_ops, bus, "pci-master-abort",
> > + memory_region_size(bus->address_space_mem));
> > + memory_region_add_subregion_overlap(bus->address_space_mem,
> > + 0, &bus->master_abort_mem,
> > + MASTER_ABORT_MEM_PRIORITY);
> > +
> > /* host bridge */
> > QLIST_INIT(&bus->child);
> >
>
> Does this handle devices behind bridges?
Yes, tested also for devices behind bridge.
>
>
> > diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
> > index 9df1788..2ad5edb 100644
> > --- a/include/hw/pci/pci_bus.h
> > +++ b/include/hw/pci/pci_bus.h
> > @@ -23,6 +23,7 @@ struct PCIBus {
> > PCIDevice *parent_dev;
> > MemoryRegion *address_space_mem;
> > MemoryRegion *address_space_io;
> > + MemoryRegion master_abort_mem;
> >
>
> Looks like this field is left uninitialized for bridge
> devices (they don't seem to call pci_bus_init)?
The bridges have no influence with respect to master_abort_mem
as it handles *all* unassigned addresses for PCI address space.
As stated above, it was tested.
Thanks,
Marcel
>
> > QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
> > QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
> > --
> > 1.8.3.1