Re: [Qemu-devel] [PATCH] target-i386: Enable x2apic by default on more r

qemu-devel

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [PATCH] target-i386: Enable x2apic by default on more r

From:	Gleb Natapov
Subject:	Re: [Qemu-devel] [PATCH] target-i386: Enable x2apic by default on more recent CPU models
Date:	Sun, 22 Sep 2013 09:36:18 +0300

On Fri, Sep 20, 2013 at 04:15:17PM -0300, Eduardo Habkost wrote:
> This enables x2apic on the following CPU models: Conroe, Penryn,
> Nehalem, Westmere, Opteron_G[12345].
> 
> Normally we try to keep the CPU model definitions as close as the real
> CPUs as possible, but x2apic can be emulated by KVM without host CPU
> support for x2apic, and it improves performance by reducing APIC access
> overhead. x2apic emulation is available on KVM since 2009 (Linux
> 2.6.32-rc1), there's no reason for not enabling x2apic by default when
> running KVM.
> 
> About testing: Conroe, Penryn, Nehalem, Westemere and Opteron_G[123]
> have x2apic enabled on RHEL-6 since RHEL-6.0, so the presence of x2apic
> on those CPU models got lots of testing in the last few years. I want to
> eventually enable x2apic on all other CPU models as well, but it will
> require some testing to ensure it won't confuse guests.
> 
> This shouldn't affect TCG at all because features not supported by TCG
> are automatically and silently disabled by QEMU when initializing the
> CPU.
> 
> Signed-off-by: Eduardo Habkost <address@hidden>
Acked-by: Gleb Natapov <address@hidden>

> ---
>  hw/i386/pc_piix.c |  9 +++++++++
>  hw/i386/pc_q35.c  |  9 +++++++++
>  target-i386/cpu.c | 37 +++++++++++++++++++------------------
>  3 files changed, 37 insertions(+), 18 deletions(-)
> 
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 907792b..0af00ef 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -240,6 +240,15 @@ static void pc_compat_1_6(QEMUMachineInitArgs *args)
>  {
>      has_pci_info = false;
>      rom_file_in_ram = false;
> +    x86_cpu_compat_set_features("Conroe", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> +    x86_cpu_compat_set_features("Penryn", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> +    x86_cpu_compat_set_features("Nehalem", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> +    x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> +    x86_cpu_compat_set_features("Opteron_G1", FEAT_1_ECX, 0, 
> CPUID_EXT_X2APIC);
> +    x86_cpu_compat_set_features("Opteron_G2", FEAT_1_ECX, 0, 
> CPUID_EXT_X2APIC);
> +    x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, 0, 
> CPUID_EXT_X2APIC);
> +    x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, 0, 
> CPUID_EXT_X2APIC);
> +    x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, 0, 
> CPUID_EXT_X2APIC);
>  }
>  
>  static void pc_compat_1_5(QEMUMachineInitArgs *args)
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index ca84e1c..82e7a23 100644
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -224,6 +224,15 @@ static void pc_compat_1_6(QEMUMachineInitArgs *args)
>  {
>      has_pci_info = false;
>      rom_file_in_ram = false;
> +    x86_cpu_compat_set_features("Conroe", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> +    x86_cpu_compat_set_features("Penryn", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> +    x86_cpu_compat_set_features("Nehalem", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> +    x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_X2APIC);
> +    x86_cpu_compat_set_features("Opteron_G1", FEAT_1_ECX, 0, 
> CPUID_EXT_X2APIC);
> +    x86_cpu_compat_set_features("Opteron_G2", FEAT_1_ECX, 0, 
> CPUID_EXT_X2APIC);
> +    x86_cpu_compat_set_features("Opteron_G3", FEAT_1_ECX, 0, 
> CPUID_EXT_X2APIC);
> +    x86_cpu_compat_set_features("Opteron_G4", FEAT_1_ECX, 0, 
> CPUID_EXT_X2APIC);
> +    x86_cpu_compat_set_features("Opteron_G5", FEAT_1_ECX, 0, 
> CPUID_EXT_X2APIC);
>  }
>  
>  static void pc_compat_1_5(QEMUMachineInitArgs *args)
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 9abb73f..23a44c3 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -791,7 +791,7 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>               CPUID_DE | CPUID_FP87,
>          .features[FEAT_1_ECX] =
> -            CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
> +            CPUID_EXT_X2APIC | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
>          .features[FEAT_8000_0001_EDX] =
>              CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
>          .features[FEAT_8000_0001_ECX] =
> @@ -813,8 +813,8 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>               CPUID_DE | CPUID_FP87,
>          .features[FEAT_1_ECX] =
> -            CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
> -             CPUID_EXT_SSE3,
> +            CPUID_EXT_X2APIC | CPUID_EXT_SSE41 | CPUID_EXT_CX16 |
> +            CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
>          .features[FEAT_8000_0001_EDX] =
>              CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
>          .features[FEAT_8000_0001_ECX] =
> @@ -836,8 +836,8 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>               CPUID_DE | CPUID_FP87,
>          .features[FEAT_1_ECX] =
> -            CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
> -             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
> +            CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
> +            CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 
> CPUID_EXT_SSE3,
>          .features[FEAT_8000_0001_EDX] =
>              CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
>          .features[FEAT_8000_0001_ECX] =
> @@ -859,9 +859,9 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>               CPUID_DE | CPUID_FP87,
>          .features[FEAT_1_ECX] =
> -            CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
> -             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
> -             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
> +            CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_X2APIC |
> +            CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 |
> +            CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
>          .features[FEAT_8000_0001_EDX] =
>              CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
>          .features[FEAT_8000_0001_ECX] =
> @@ -943,7 +943,7 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>               CPUID_DE | CPUID_FP87,
>          .features[FEAT_1_ECX] =
> -            CPUID_EXT_SSE3,
> +            CPUID_EXT_X2APIC | CPUID_EXT_SSE3,
>          .features[FEAT_8000_0001_EDX] =
>              CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
>               CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
> @@ -968,7 +968,7 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>               CPUID_DE | CPUID_FP87,
>          .features[FEAT_1_ECX] =
> -            CPUID_EXT_CX16 | CPUID_EXT_SSE3,
> +            CPUID_EXT_X2APIC | CPUID_EXT_CX16 | CPUID_EXT_SSE3,
>          .features[FEAT_8000_0001_EDX] =
>              CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
>               CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
> @@ -996,8 +996,8 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
>               CPUID_DE | CPUID_FP87,
>          .features[FEAT_1_ECX] =
> -            CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
> -             CPUID_EXT_SSE3,
> +            CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_CX16 |
> +            CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
>          .features[FEAT_8000_0001_EDX] =
>              CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
>               CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
> @@ -1027,9 +1027,9 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_DE | CPUID_FP87,
>          .features[FEAT_1_ECX] =
>              CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
> -             CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
> -             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
> -             CPUID_EXT_SSE3,
> +             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
> +             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
> +             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
>          .features[FEAT_8000_0001_EDX] =
>              CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
>               CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
> @@ -1061,9 +1061,10 @@ static x86_def_t builtin_x86_defs[] = {
>               CPUID_DE | CPUID_FP87,
>          .features[FEAT_1_ECX] =
>              CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
> -             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
> -             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
> -             CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
> +             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_X2APIC |
> +             CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 |
> +             CPUID_EXT_FMA | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
> +             CPUID_EXT_SSE3,
>          .features[FEAT_8000_0001_EDX] =
>              CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
>               CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
> -- 
> 1.8.3.1

--
                        Gleb.

[Prev in Thread]

Current Thread

[Next in Thread]

[Qemu-devel] [PATCH] target-i386: Enable x2apic by default on more recent CPU models, Eduardo Habkost, 2013/09/20
- Re: [Qemu-devel] [PATCH] target-i386: Enable x2apic by default on more recent CPU models, Gleb Natapov <=

Prev by Date: Re: [Qemu-devel] in_asm substitute for accel=kvm:tcg
Next by Date: Re: [Qemu-devel] [PATCH V4 0/3] qemu-iotests: add test for fd passing via SCM rights
Previous by thread: [Qemu-devel] [PATCH] target-i386: Enable x2apic by default on more recent CPU models
Next by thread: [Qemu-devel] [PATCH] block: introduce BlockDriver.bdrv_needs_filename to enable some drivers.
Index(es):
- Date
- Thread