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[Qemu-devel] [PATCH 28/60] AArch64: Add movi instruction emulation
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PATCH 28/60] AArch64: Add movi instruction emulation |
Date: |
Fri, 27 Sep 2013 02:48:22 +0200 |
This patch adds emulation for the movi instruction.
Signed-off-by: Alexander Graf <address@hidden>
---
target-arm/translate-a64.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index c5d0def..e4f0306 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1011,6 +1011,44 @@ static void handle_addi(DisasContext *s, uint32_t insn)
}
+static void handle_movi(DisasContext *s, uint32_t insn)
+{
+ int reg = get_reg(insn);
+ uint64_t imm = get_bits(insn, 5, 16);
+ int is_32bit = !get_bits(insn, 31, 1);
+ int is_k = get_bits(insn, 29, 1);
+ int is_n = !get_bits(insn, 30, 1);
+ int pos = get_bits(insn, 21, 2) << 4;
+ TCGv_i64 tcg_imm;
+
+ if (get_bits(insn, 23, 1) != 1) {
+ /* reserved */
+ unallocated_encoding(s);
+ return;
+ }
+
+ if (is_k && is_n) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ if (is_k) {
+ tcg_imm = tcg_const_i64(imm);
+ tcg_gen_deposit_i64(cpu_reg(reg), cpu_reg(reg), tcg_imm, pos, 16);
+ tcg_temp_free_i64(tcg_imm);
+ } else {
+ tcg_gen_movi_i64(cpu_reg(reg), imm << pos);
+ }
+
+ if (is_n) {
+ tcg_gen_not_i64(cpu_reg(reg), cpu_reg(reg));
+ }
+
+ if (is_32bit) {
+ tcg_gen_ext32u_i64(cpu_reg(reg), cpu_reg(reg));
+ }
+}
+
/* SIMD ORR */
static void handle_simdorr(DisasContext *s, uint32_t insn)
{
@@ -1439,6 +1477,13 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s)
case 0x11:
handle_addi(s, insn);
break;
+ case 0x12:
+ if (get_bits(insn, 23, 1)) {
+ handle_movi(s, insn);
+ } else {
+ unallocated_encoding(s);
+ }
+ break;
default:
unallocated_encoding(s);
break;
--
1.7.12.4
- [Qemu-devel] [PATCH 24/60] AArch64: Add SIMD ushll instruction emulation, (continued)
- [Qemu-devel] [PATCH 24/60] AArch64: Add SIMD ushll instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 26/60] AArch64: Add ADR instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 20/60] AArch64: Add SIMD ORR family instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 18/60] AArch64: Add umov instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 03/60] arm: Split VFP cmp from FPSCR setting, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 28/60] AArch64: Add movi instruction emulation,
Alexander Graf <=
- [Qemu-devel] [PATCH 16/60] AArch64: Add emulation for SIMD ld/st multiple, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 27/60] AArch64: Add addi instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 25/60] AArch64: Add SIMD shl instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 30/60] AArch64: Add extr instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 29/60] AArch64: Add orri instruction emulation, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 23/60] AArch64: Add AdvSIMD modified immediate group handling, Alexander Graf, 2013/09/26
- [Qemu-devel] [PATCH 31/60] AArch64: Add bfm family instruction emulation, Alexander Graf, 2013/09/26