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From: | Stefan Kristiansson |
Subject: | Re: [Qemu-devel] [OpenRISC] [PATCH] Correction of the TLB handling of the OpenRISC target |
Date: | Wed, 2 Oct 2013 09:15:28 +0300 |
Hi Sebastian,
@@ -102,7 +102,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
On Wed, Oct 2, 2013 at 1:12 PM, Sebastian Macke <address@hidden> wrote:
> Hi,
>
> this patch corrects two problems for the OpenRISC Target in QEMU. The first
> one corrects one obvious bug
> concerning the handling of page faults while reading from a page.
}
}
- if ((rw & 0) && ((right & PAGE_READ) == 0)) {
+ if (!(rw & 1) && ((right & PAGE_READ) == 0)) {
return TLBRET_BADADDR;
}
if ((rw & 1) && ((right & PAGE_WRITE) == 0)) {
They are just two type of one code...
@@ -122,13 +122,6 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu,
> The second
> part removes a non-conforming behavior for the first page of the memory.
{
int ret = TLBRET_MATCH;
- /* [0x0000--0x2000]: unmapped */
- if (address < 0x2000 && (cpu->env.sr & SR_SM)) {
- *physical = address;
- *prot = PAGE_READ | PAGE_WRITE;
- return ret;
- }
-
May you please explain more about why the first page is non-conforming?
The Arch manual told me 0x0000--0x2000 is unmapped.
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