Re: [Qemu-devel] [PATCH 1/1] sd: pl181: fix fifo count read support

[Jean-Christophe PLAGNIOL-VILLARD]

On 18:44 Fri 25 Oct     , Peter Maydell wrote:
> On 25 October 2013 12:04, Jean-Christophe PLAGNIOL-VILLARD
> <address@hidden> wrote:
> > On 11:33 Sat 19 Oct     , Jean-Christophe PLAGNIOL-VILLARD wrote:
> >> as it's depend on current direction
> >
> > ony change to get that applied?
> >
> > Barebox relay on it so it can work on both qemu and real hw
> 
> I can't see anything obvious in the PL181 data sheet that
> says this register should change behaviour like this based
> on the direction of transfer, so I'm afraid I can't accept
> this patch without a much more detailed analysis of why
> it is correct. (Just as a for-starters, how does this change
> relate to the comment immediately above that mentions vagueness
> in the documentation and claims we don't need to emulate things
> to an exact level of detail? Is this change supposed to fix
> that? Does the comment need to change? Which bit of the
> PL181 documentation describes the behaviour the patch is
> affecting? etc)

it's

the register is supposed to report the status of the fifo

and in qemu if always report the datacnt which is the number of byte to
write and in case of reading it's always 0 so bootloader that use polling will
never be get any data.

And yes the readl hw does report the fifo lenght in case of read and write
not always 0 when reading.

Best Regards,
J.