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Re: [Qemu-devel] [PATCH 03/13] target-openrisc: Separate of load/store i


From: Sebastian Macke
Subject: Re: [Qemu-devel] [PATCH 03/13] target-openrisc: Separate of load/store instructions
Date: Tue, 29 Oct 2013 16:37:05 -0700
User-agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.0.1

On 29/10/2013 3:55 PM, Max Filippov wrote:
On Wed, Oct 30, 2013 at 1:36 AM, Sebastian Macke <address@hidden> wrote:
On 29/10/2013 1:05 PM, Max Filippov wrote:
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke <address@hidden>
wrote:
Additional this patch solves a severe bug for the softmmu emulation.
The pc has to be saved as these instructions can fail and lead
to a tlb miss exception.
In case of an exception we re-translate the TB to find the PC where
the exception happened, see cpu_restore_state call from the tlb_fill
function. Also this applies to both user and system emulation, but
you only handle the system emulation case.
The problem is the epcr register in the interrupt routine in which the
current pc must be saved.
Of course in the user emulation case the interrupt handler is never
executed.

When is the pc of the fault determined? Before or after the interrupt
handler?
Before, in the tlb_fill: cpu_restore_state is called to restore context,
and after that cpu_loop_exit is called to handle the exception.

Ok, but then my line should be useless and the pc value should be immediately overwritten when the we get an OpenRISC TLB miss. This is definitely not the case. If I remove it I get random kernel crashes. So there is anything else wrong. Maybe the curent MMU code directly executes the exception handler. So QEMU has no chance in interfering and can't give me the correct pc. Maybe I will have to restore the context myself.

Finding this problem gave me a long headache. But it would be nice if there
is a better solution.




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