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[Qemu-devel] [PULL 0/7] OpenRISC patch queue for 1.7
From: |
Jia Liu |
Subject: |
[Qemu-devel] [PULL 0/7] OpenRISC patch queue for 1.7 |
Date: |
Wed, 20 Nov 2013 22:38:31 +0800 |
Hi Anthony,
Hi Blue,
This is my OpenRISC patch queue for 1.7, it have been well tested, please pull.
Thanks to Sebastian Macke, it made move optimization and fix some bugs.
The following changes since commit 394cfa39ba24dd838ace1308ae24961243947fb8:
Merge remote-tracking branch 'quintela/migration.next' into staging
(2013-11-19 13:03:06 -0800)
are available in the git repository at:
git://github.com/J-Liu/qemu.git or32
for you to fetch changes up to 14a650ec25ca93a626397783d6c6e840ec2502c6:
target-openrisc: Correct carry flag check of l.addc and l.addic test cases
(2013-11-20 21:47:46 +0800)
----------------------------------------------------------------
Sebastian Macke (7):
target-openrisc: Speed up move instruction
target-openrisc: Remove unnecessary code generated by jump instructions
target-openrisc: Remove executable flag for every page
target-openrisc: Correct wrong epcr register in interrupt handler
openrisc-timer: Reduce overhead, Separate clock update functions
target-openrisc: Correct memory bounds checking for the tlb buffers
target-openrisc: Correct carry flag check of l.addc and l.addic test cases
hw/openrisc/cputimer.c | 29 ++++++++-----
target-openrisc/cpu.h | 1 +
target-openrisc/interrupt.c | 25 +++--------
target-openrisc/mmu.c | 4 +-
target-openrisc/sys_helper.c | 54 +++++++++++------------
target-openrisc/translate.c | 95 +++++++++++++++++++++++------------------
tests/tcg/openrisc/test_addc.c | 8 ++--
tests/tcg/openrisc/test_addic.c | 10 +++--
8 files changed, 119 insertions(+), 107 deletions(-)
- [Qemu-devel] [PULL 0/7] OpenRISC patch queue for 1.7,
Jia Liu <=
- [Qemu-devel] [PULL 3/7] target-openrisc: Remove executable flag for every page, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 4/7] target-openrisc: Correct wrong epcr register in interrupt handler, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 5/7] openrisc-timer: Reduce overhead, Separate clock update functions, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 6/7] target-openrisc: Correct memory bounds checking for the tlb buffers, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 7/7] target-openrisc: Correct carry flag check of l.addc and l.addic test cases, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 1/7] target-openrisc: Speed up move instruction, Jia Liu, 2013/11/20
- [Qemu-devel] [PULL 2/7] target-openrisc: Remove unnecessary code generated by jump instructions, Jia Liu, 2013/11/20