From 9cf2af82399d7d7a9717ff6ac17860b66c705a64 Mon Sep 17 00:00:00 2001 From: Laszlo Ersek Date: Tue, 19 Nov 2013 13:07:41 +0100 Subject: [PATCH] OvmfPkg/PlatformPei: follow SeaBIOS tradition with 32-bit PCI hole placement Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/PlatformPei/Platform.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index fb56e99..5bc0d74 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -197,7 +197,7 @@ MemMapInitialization ( // // address purpose size // ------------ -------- ------------------------- - // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) + // 2G/3G/3.5G PCI MMIO 0xFC000000 - 2G/3G/3.5G // 0xFC000000 gap 44 MB // 0xFEC00000 IO-APIC 4 KB // 0xFEC01000 gap 1020 KB @@ -205,7 +205,9 @@ MemMapInitialization ( // 0xFED00400 gap 1023 KB // 0xFEE00000 LAPIC 1 MB // - AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFC000000); + AddIoMemoryRangeHob (TopOfMemory <= 0x80000000 ? 0x80000000 : + TopOfMemory <= 0xC0000000 ? 0xC0000000 : + 0xE0000000, 0xFC000000); AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB); -- 1.8.3.1