[Qemu-devel] [RFC PATCH 05/21] target-arm: add CPU Monitor mode

[Sergey Fedorov]

From: Svetlana Fedoseeva <address@hidden>

Define CPU monitor mode. Adjust core registers banking. Adjust CPU VM
state info. Provide CPU mode name for monitor mode.

Signed-off-by: Svetlana Fedoseeva <address@hidden>
Signed-off-by: Sergey Fedorov <address@hidden>
---
 target-arm/cpu.h       |    7 ++++---
 target-arm/helper.c    |    3 +++
 target-arm/machine.c   |   12 ++++++------
 target-arm/translate.c |    2 +-
 4 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 0b93e39..94d8bd1 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -124,9 +124,9 @@ typedef struct CPUARMState {
     uint32_t spsr;
 
     /* Banked registers.  */
-    uint32_t banked_spsr[6];
-    uint32_t banked_r13[6];
-    uint32_t banked_r14[6];
+    uint32_t banked_spsr[7];
+    uint32_t banked_r13[7];
+    uint32_t banked_r14[7];
 
     /* These hold r8-r12.  */
     uint32_t usr_regs[5];
@@ -402,6 +402,7 @@ enum arm_cpu_mode {
   ARM_CPU_MODE_FIQ = 0x11,
   ARM_CPU_MODE_IRQ = 0x12,
   ARM_CPU_MODE_SVC = 0x13,
+  ARM_CPU_MODE_MON = 0x16,
   ARM_CPU_MODE_ABT = 0x17,
   ARM_CPU_MODE_UND = 0x1b,
   ARM_CPU_MODE_SYS = 0x1f
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d7922ad..d4407cf 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2018,6 +2018,7 @@ static int bad_mode_switch(CPUARMState *env, int mode)
     case ARM_CPU_MODE_USR:
     case ARM_CPU_MODE_SYS:
     case ARM_CPU_MODE_SVC:
+    case ARM_CPU_MODE_MON:
     case ARM_CPU_MODE_ABT:
     case ARM_CPU_MODE_UND:
     case ARM_CPU_MODE_IRQ:
@@ -2202,6 +2203,8 @@ int bank_number(int mode)
         return 4;
     case ARM_CPU_MODE_FIQ:
         return 5;
+    case ARM_CPU_MODE_MON:
+        return 6;
     }
     hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
 }
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 74f010f..51d0c79 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -222,9 +222,9 @@ static int cpu_post_load(void *opaque, int version_id)
 
 const VMStateDescription vmstate_arm_cpu = {
     .name = "cpu",
-    .version_id = 13,
-    .minimum_version_id = 13,
-    .minimum_version_id_old = 13,
+    .version_id = 14,
+    .minimum_version_id = 14,
+    .minimum_version_id_old = 14,
     .pre_save = cpu_pre_save,
     .post_load = cpu_post_load,
     .fields = (VMStateField[]) {
@@ -238,9 +238,9 @@ const VMStateDescription vmstate_arm_cpu = {
             .offset = 0,
         },
         VMSTATE_UINT32(env.spsr, ARMCPU),
-        VMSTATE_UINT32_ARRAY(env.banked_spsr, ARMCPU, 6),
-        VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6),
-        VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
+        VMSTATE_UINT32_ARRAY(env.banked_spsr, ARMCPU, 7),
+        VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 7),
+        VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 7),
         VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
         VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
         /* The length-check must come before the arrays to avoid
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 5f003e7..665c8ac 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -10295,7 +10295,7 @@ void gen_intermediate_code_pc(CPUARMState *env, 
TranslationBlock *tb)
 }
 
 static const char *cpu_mode_names[16] = {
-  "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
+  "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
   "???", "???", "???", "und", "???", "???", "???", "sys"
 };
 
-- 
1.7.9.5