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[Qemu-devel] [PATCH 00/13] target-arm: A64 decoder set 2: misc logic and
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 00/13] target-arm: A64 decoder set 2: misc logic and bit ops |
Date: |
Thu, 5 Dec 2013 21:51:16 +0000 |
The first chunk of A64 decoder patches have now made it through
code review, so as promised here's the next chunk. This is a
grabbag of miscellaneous logic and bit-twiddling operations,
plus some other minor stuff like ADR and conditional-select.
(Set three is probably going to be loads and stores. Set four
is likely to be 'everything else needed to run a simple binary':
add/sub, multiplies, the user-space visible MRS/MSR registers, svc,
fp<->integer register moves and the exclusive load/store group,
though that might get split into 'four' and 'five' sets if it's
not all cooked by the time 'three' gets through patch review.
Following that in some order should be VFP, Neon, and anything
that fell through the cracks (adc, anybody?).)
Git tree (with v7-cpu-host/mach-virt, v8 kvm control,
and A64 set one all underneath these ptaches):
git://git.linaro.org/people/pmaydell/qemu-arm.git a64-second-set
web UI:
https://git.linaro.org/gitweb?p=people/pmaydell/qemu-arm.git;a=shortlog;h=refs/heads/a64-second-set
Alexander Graf (7):
target-arm: A64: add support for logical (shifted register)
target-arm: A64: add support for ADR and ADRP
target-arm: A64: add support for EXTR
target-arm: A64: add support for 2-src data processing and DIV
target-arm: A64: add support for 2-src shift reg insns
target-arm: A64: add support for 1-src RBIT insn
target-arm: A64: add support for logical (immediate) insns
Claudio Fontana (6):
target-arm: A64: add support for conditional select
target-arm: A64: add support for 1-src data processing and CLZ
target-arm: A64: add support for 1-src REV insns
target-arm: A64: add support for bitfield insns
host-utils: add clrsb32/64 - count leading redundant sign bits
target-arm: A64: add support for 1-src CLS insn
include/qemu/host-utils.h | 32 ++
target-arm/helper-a64.c | 54 +++
target-arm/helper-a64.h | 6 +
target-arm/translate-a64.c | 783 ++++++++++++++++++++++++++++++++++++++++++--
4 files changed, 855 insertions(+), 20 deletions(-)
--
1.7.9.5
- [Qemu-devel] [PATCH 00/13] target-arm: A64 decoder set 2: misc logic and bit ops,
Peter Maydell <=
- [Qemu-devel] [PATCH 08/13] target-arm: A64: add support for 1-src RBIT insn, Peter Maydell, 2013/12/05
- [Qemu-devel] [PATCH 10/13] target-arm: A64: add support for bitfield insns, Peter Maydell, 2013/12/05
- [Qemu-devel] [PATCH 13/13] target-arm: A64: add support for logical (immediate) insns, Peter Maydell, 2013/12/05
- [Qemu-devel] [PATCH 04/13] target-arm: A64: add support for EXTR, Peter Maydell, 2013/12/05
- [Qemu-devel] [PATCH 01/13] target-arm: A64: add support for conditional select, Peter Maydell, 2013/12/05