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Re: [Qemu-devel] [PATCH 05/13] target-arm: A64: add support for 2-src da
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 05/13] target-arm: A64: add support for 2-src data processing and DIV |
Date: |
Thu, 5 Dec 2013 23:09:23 +0000 |
On 5 December 2013 22:51, Richard Henderson <address@hidden> wrote:
> On 12/06/2013 10:51 AM, Peter Maydell wrote:
>> + switch (opcode) {
>> + case 2: /* UDIV */
>> + handle_div(s, FALSE, sf, rm, rn, rd);
>> + break;
>> + case 3: /* SDIV */
>> + handle_div(s, TRUE, sf, rm, rn, rd);
>> + break;
>
> What are these all-caps TRUE/FALSE? stdbool.h uses lower-case.
Good question, I wonder what system header is managing to define
those for us? (there are some other bits of the source tree which
use them too I see).
> Otherwise,
>
> Reviewed-by: Richard Henderson <address@hidden>
By the way, for these "otherwise reviewed-by" patches, would
you prefer me to make the obvious trivial fix and include your
R-b tag on the fixed version in the next respin, or to make the
fix and leave the tag off so you can recheck it?
thanks
-- PMM
- Re: [Qemu-devel] [PATCH 01/13] target-arm: A64: add support for conditional select, (continued)
[Qemu-devel] [PATCH 11/13] host-utils: add clrsb32/64 - count leading redundant sign bits, Peter Maydell, 2013/12/05
[Qemu-devel] [PATCH 07/13] target-arm: A64: add support for 1-src data processing and CLZ, Peter Maydell, 2013/12/05
[Qemu-devel] [PATCH 05/13] target-arm: A64: add support for 2-src data processing and DIV, Peter Maydell, 2013/12/05
[Qemu-devel] [PATCH 03/13] target-arm: A64: add support for ADR and ADRP, Peter Maydell, 2013/12/05
[Qemu-devel] [PATCH 06/13] target-arm: A64: add support for 2-src shift reg insns, Peter Maydell, 2013/12/05
[Qemu-devel] [PATCH 02/13] target-arm: A64: add support for logical (shifted register), Peter Maydell, 2013/12/05