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[Qemu-devel] [PULL 37/37] target-arm: fix TTBCR write masking
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 37/37] target-arm: fix TTBCR write masking |
Date: |
Tue, 10 Dec 2013 14:43:33 +0000 |
From: Sergey Fedorov <address@hidden>
Current implementation is not accurate according to ARMv7-AR reference
manual. See "B4.1.153 TTBCR, Translation Table Base Control Register,
VMSA | TTBCR format when using the Long-descriptor translation table
format". When LPAE feature is supported, EAE, bit[31] selects
translation descriptor format and, therefore, TTBCR format.
Signed-off-by: Sergey Fedorov <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 8ec4cb1..5e5e5aa 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1173,7 +1173,7 @@ static int vmsa_ttbcr_raw_write(CPUARMState *env, const
ARMCPRegInfo *ri,
{
int maskshift = extract32(value, 0, 3);
- if (arm_feature(env, ARM_FEATURE_LPAE)) {
+ if (arm_feature(env, ARM_FEATURE_LPAE) && (value & (1 << 31))) {
value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
} else {
value &= 7;
--
1.8.5
- [Qemu-devel] [PULL 07/37] device_tree.c: Terminate the empty reservemap in create_device_tree(), (continued)
- [Qemu-devel] [PULL 07/37] device_tree.c: Terminate the empty reservemap in create_device_tree(), Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 04/37] hw/timer: Introduce ARM A9 Global Timer., Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 20/37] net/cadence_gem: Prefetch rx descriptors ASAP, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 01/37] integrator/cp: add support for REFCNT register, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 05/37] cpu/a9mpcore: Add Global Timer, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 08/37] hw/arm/boot: Allow boards to provide an fdt blob, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 23/37] net/cadence_gem: Implement SAR (de)activation, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 14/37] target-arm: Provide '-cpu host' when running KVM, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 13/37] target-arm: Don't hardcode KVM target CPU to be A15, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 21/37] net/cadence_gem: Implement RX descriptor match mode flags, Peter Maydell, 2013/12/10
- [Qemu-devel] [PULL 37/37] target-arm: fix TTBCR write masking,
Peter Maydell <=
- [Qemu-devel] [PULL 18/37] net/cadence_gem: Don't assert against 0 buffer address, Peter Maydell, 2013/12/10