[Qemu-devel] [PATCH 00/21] target-arm: A64 decoder sets 3 and 4: everything but fp & simd

[Peter Maydell]

Hi; the a64-third-set patches haven't all made it through
review yet, but I thought it was worth adding my fourth set
of patches into them, because with these patches we have
support for pretty much all instructions except:
 * FP [we support simple FP register load/store and
   transfer to/from the general purpose registers]
 * Neon
 * system instructions (either ones only available to system
   mode or which only make sense for system mode like LDRT)
(There may also be one or two obscure gaps like the CRC32 instruction.)

So this patchset includes the default-config that enables
building the aarch64-linux target.

This patchset includes support for MRS/MSR for the handful
of registers which are accessible in user mode. I've
replaced the simple user-mode-only implementation in the
initial SuSE patches with a proper integration into the
cpregs hashtable infrastructure, because we're going to need
that for system mode anyway.

The ld/st exclusive code has also been reworked slightly
so that the AArch32 and AArch64 sides coexist a bit more
cleanly.

This patchset sits on top of target-arm.next; git tree
available at:
 git://git.linaro.org/people/peter.maydell/qemu-arm.git a64-third-fourth-set
web UI:
 
https://git.linaro.org/people/peter.maydell/qemu-arm.git/shortlog/refs/heads/a64-third-fourth-set

Review welcomed, though I appreciate that we're heading
down towards the Christmas lull...

thanks
-- PMM

Alex Bennée (6):
  target-arm: A64: add support for ld/st pair
  target-arm: A64: add support for ld/st unsigned imm
  target-arm: A64: add support for ld/st with reg offset
  target-arm: A64: add support for ld/st with index
  target-arm: A64: add support for add, addi, sub, subi
  target-arm: A64: add support for move wide instructions

Alexander Graf (3):
  target-arm: A64: add support for 3 src data proc insns
  target-arm: A64: implement SVC, BRK
  target-arm: aarch64: add support for ld lit

Claudio Fontana (2):
  target-arm: A64: add support for add/sub with carry
  target-arm: A64: add support for conditional compare insns

Michael Matz (1):
  target-arm: A64: support for ld/st/cl exclusive

Peter Maydell (9):
  target-arm: A64: Add decoder skeleton for FP instructions
  target-arm: A64: implement FMOV
  target-arm: Update generic cpreg code for AArch64
  target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder
  target-arm: A64: Implement MRS/MSR/SYS/SYSL
  target-arm: A64: Implement minimal set of EL0-visible sysregs
  target-arm: Widen thread-local register state fields to 64 bits
  target-arm: Widen exclusive-access support struct fields to 64 bits
  default-configs: Add config for aarch64-linux-user

 default-configs/aarch64-linux-user.mak |    3 +
 linux-user/aarch64/target_cpu.h        |    5 +-
 linux-user/arm/target_cpu.h            |    2 +-
 linux-user/main.c                      |  154 ++-
 target-arm/cpu.h                       |   94 +-
 target-arm/helper.c                    |  151 ++-
 target-arm/kvm-consts.h                |   37 +
 target-arm/machine.c                   |   12 +-
 target-arm/translate-a64.c             | 1927 +++++++++++++++++++++++++++++++-
 target-arm/translate.c                 |   72 +-
 target-arm/translate.h                 |    2 +
 11 files changed, 2320 insertions(+), 139 deletions(-)
 create mode 100644 default-configs/aarch64-linux-user.mak

-- 
1.8.5