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[Qemu-devel] [PULL 45/62] target-arm: A64: add support for 1-src RBIT in
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 45/62] target-arm: A64: add support for 1-src RBIT insn |
Date: |
Tue, 17 Dec 2013 20:29:03 +0000 |
From: Alexander Graf <address@hidden>
This adds support for the C5.6.147 RBIT instruction.
Signed-off-by: Alexander Graf <address@hidden>
[claudio: adapted to new decoder, use bswap64,
make RBIT part standalone from the rest of the patch,
splitting REV into a separate patch]
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-arm/helper-a64.c | 18 ++++++++++++++++++
target-arm/helper-a64.h | 1 +
target-arm/translate-a64.c | 20 ++++++++++++++++++++
3 files changed, 39 insertions(+)
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index e4c5346..cccaac6 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -49,3 +49,21 @@ uint64_t HELPER(clz64)(uint64_t x)
{
return clz64(x);
}
+
+uint64_t HELPER(rbit64)(uint64_t x)
+{
+ /* assign the correct byte position */
+ x = bswap64(x);
+
+ /* assign the correct nibble position */
+ x = ((x & 0xf0f0f0f0f0f0f0f0ULL) >> 4)
+ | ((x & 0x0f0f0f0f0f0f0f0fULL) << 4);
+
+ /* assign the correct bit position */
+ x = ((x & 0x8888888888888888ULL) >> 3)
+ | ((x & 0x4444444444444444ULL) >> 1)
+ | ((x & 0x2222222222222222ULL) << 1)
+ | ((x & 0x1111111111111111ULL) << 3);
+
+ return x;
+}
diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h
index b10b6c3..9959139 100644
--- a/target-arm/helper-a64.h
+++ b/target-arm/helper-a64.h
@@ -19,3 +19,4 @@
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
DEF_HELPER_FLAGS_1(clz64, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index e5481da..0ed21fc 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1062,6 +1062,24 @@ static void handle_clz(DisasContext *s, unsigned int sf,
}
}
+static void handle_rbit(DisasContext *s, unsigned int sf,
+ unsigned int rn, unsigned int rd)
+{
+ TCGv_i64 tcg_rd, tcg_rn;
+ tcg_rd = cpu_reg(s, rd);
+ tcg_rn = cpu_reg(s, rn);
+
+ if (sf) {
+ gen_helper_rbit64(tcg_rd, tcg_rn);
+ } else {
+ TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
+ tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn);
+ gen_helper_rbit(tcg_tmp32, tcg_tmp32);
+ tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
+ tcg_temp_free_i32(tcg_tmp32);
+ }
+}
+
/* C3.5.7 Data-processing (1 source)
* 31 30 29 28 21 20 16 15 10 9 5 4 0
* +----+---+---+-----------------+---------+--------+------+------+
@@ -1084,6 +1102,8 @@ static void disas_data_proc_1src(DisasContext *s,
uint32_t insn)
switch (opcode) {
case 0: /* RBIT */
+ handle_rbit(s, sf, rn, rd);
+ break;
case 1: /* REV16 */
case 2: /* REV32 */
case 3: /* REV64 */
--
1.8.5
- [Qemu-devel] [PULL 00/62] target-arm queue, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 08/62] Fix NOR flash device ID reading, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 56/62] MAINTAINERS: Document 'Canon DIGIC' machine, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 40/62] target-arm: A64: add support for ADR and ADRP, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 62/62] MAINTAINERS: add myself to maintain allwinner-a10, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 51/62] hw/arm: add very initial support for Canon DIGIC SoC, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 50/62] target-arm: A64: add support for logical (immediate) insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 10/62] target-arm: Define and use ARM_FEATURE_CBAR, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 42/62] target-arm: A64: add support for 2-src data processing and DIV, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 45/62] target-arm: A64: add support for 1-src RBIT insn,
Peter Maydell <=
- [Qemu-devel] [PULL 53/62] hw/arm/digic: add timer support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 58/62] hw/timer: add allwinner a10 timer, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 52/62] hw/arm/digic: prepare DIGIC-based boards support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 48/62] host-utils: add clrsb32/64 - count leading redundant sign bits, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 47/62] target-arm: A64: add support for bitfield insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 46/62] target-arm: A64: add support for 1-src REV insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 54/62] hw/arm/digic: add UART support, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 43/62] target-arm: A64: add support for 2-src shift reg insns, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 37/62] target-arm: A64: add support for compare and branch imm, Peter Maydell, 2013/12/17
- [Qemu-devel] [PULL 59/62] hw/intc: add allwinner A10 interrupt controller, Peter Maydell, 2013/12/17