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Re: [Qemu-devel] [PATCH 01/11] acpi: piix4: remove not needed GPE0 mask
From: |
Michael S. Tsirkin |
Subject: |
Re: [Qemu-devel] [PATCH 01/11] acpi: piix4: remove not needed GPE0 mask |
Date: |
Thu, 19 Dec 2013 16:16:18 +0200 |
On Fri, Dec 13, 2013 at 05:22:06PM +0100, Igor Mammedov wrote:
> Hardcoded GPE0 mask isn't really needed. Since GPE0_STS initialized
> with all bits cleared and only QEMU itself can set bits there (i.e.
> guest can only clear bits in it). So guest can't triger SCI
> by setting _STS & _EN bits and there is not reason to mask out not
> supported _STS bits since they shouldn't be set by QEMU in the first
> place.
>
> Signed-off-by: Igor Mammedov <address@hidden>
Applied, thanks.
> ---
> hw/acpi/piix4.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> index 93849c8..b4caeab 100644
> --- a/hw/acpi/piix4.c
> +++ b/hw/acpi/piix4.c
> @@ -122,8 +122,7 @@ static void pm_update_sci(PIIX4PMState *s)
> ACPI_BITMASK_POWER_BUTTON_ENABLE |
> ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
> ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
> - (((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) &
> - (PIIX4_PCI_HOTPLUG_STATUS | PIIX4_CPU_HOTPLUG_STATUS)) != 0);
> + ((s->ar.gpe.sts[0] & s->ar.gpe.en[0]) != 0);
>
> qemu_set_irq(s->irq, sci_level);
> /* schedule a timer interruption if needed */
> --
> 1.8.3.1