Re: [Qemu-devel] [PATCH] target-arm: use c13_context field for CONTEXTIDR

[Peter Crosthwaite]

On Fri, Dec 20, 2013 at 8:04 PM, Peter Maydell <address@hidden> wrote:
> On 20 December 2013 06:33, Sergey Fedorov <address@hidden> wrote:
>> Use c13_context field instead of c13_fcse for CONTEXTIDR register
>> definition.
>>
>> Signed-off-by: Sergey Fedorov <address@hidden>
>> Reviewed-by: Peter Crosthwaite <address@hidden>
>> ---
>>  target-arm/helper.c |    2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target-arm/helper.c b/target-arm/helper.c
>> index 6ebd7dc..d52da0a 100644
>> --- a/target-arm/helper.c
>> +++ b/target-arm/helper.c
>> @@ -397,7 +397,7 @@ static const ARMCPRegInfo cp_reginfo[] = {
>>        .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
>>        .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
>>      { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 
>> = 1,
>> -      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
>> +      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, 
>> cp15.c13_context),
>>        .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = 
>> raw_write, },
>>      /* ??? This covers not just the impdef TLB lockdown registers but also
>>       * some v7VMSA registers relating to TEX remap, so it is overly broad.
>
> Wow, I wonder how things worked with that broken. Obvious cut-n-paste
> damage from back when we converted the cp regs.
>

Has a custom write handler which is correct AFAIK, so a write only
guest will work :)

Regards,
Peter

> Reviewed-by: Peter Maydell <address@hidden>
>
> thanks
> -- PMM
>