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Re: [Qemu-devel] [PATCH 13/21] target-arm: A64: Implement MRS/MSR/SYS/SY
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 13/21] target-arm: A64: Implement MRS/MSR/SYS/SYSL |
Date: |
Fri, 20 Dec 2013 13:27:31 +0000 |
On 19 December 2013 20:30, Richard Henderson <address@hidden> wrote:
> On 12/17/2013 07:12 AM, Peter Maydell wrote:
>> +/* Force a TB lookup after an instruction that changes the CPU state */
>> +static inline void gen_lookup_tb(DisasContext *s)
>> +{
>> + gen_a64_set_pc_im(s->pc);
>> + s->is_jmp = DISAS_UPDATE;
>> +}
>> +
>
> I'm a bit surprised that this set_pc doesn't happen in
> gen_intermediate_code_internal_a64. Otherwise, what's the point in
> distinguishing between DISAS_JUMP and DISAS_UPDATE?
I just borrowed this from the 32 bit decoder, which also sets PC
in gen_lookup_tb(). However you're right that we might as well
do the set pc in the top level loop. I've adjusted that loop to do so
and dropped the gen_lookup_tb() function in favour of just setting
s->is_jmp = DISAS_UPDATE directly at its callsites.
thanks
-- PMM
- Re: [Qemu-devel] [PATCH 02/21] target-arm: A64: add support for ld/st unsigned imm, (continued)
- [Qemu-devel] [PATCH 10/21] target-arm: A64: implement FMOV, Peter Maydell, 2013/12/17
- [Qemu-devel] [PATCH 19/21] target-arm: Widen exclusive-access support struct fields to 64 bits, Peter Maydell, 2013/12/17
- [Qemu-devel] [PATCH 21/21] default-configs: Add config for aarch64-linux-user, Peter Maydell, 2013/12/17
- [Qemu-devel] [PATCH 04/21] target-arm: A64: add support for ld/st with index, Peter Maydell, 2013/12/17
- [Qemu-devel] [PATCH 08/21] target-arm: A64: implement SVC, BRK, Peter Maydell, 2013/12/17
- [Qemu-devel] [PATCH 13/21] target-arm: A64: Implement MRS/MSR/SYS/SYSL, Peter Maydell, 2013/12/17
- [Qemu-devel] [PATCH 20/21] target-arm: A64: support for ld/st/cl exclusive, Peter Maydell, 2013/12/17
- [Qemu-devel] [PATCH 16/21] target-arm: A64: add support for add/sub with carry, Peter Maydell, 2013/12/17
- [Qemu-devel] [PATCH 03/21] target-arm: A64: add support for ld/st with reg offset, Peter Maydell, 2013/12/17
- [Qemu-devel] [PATCH 09/21] target-arm: A64: Add decoder skeleton for FP instructions, Peter Maydell, 2013/12/17
- [Qemu-devel] [PATCH 15/21] target-arm: Widen thread-local register state fields to 64 bits, Peter Maydell, 2013/12/17