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Re: [Qemu-devel] [PATCH 02/21] target-arm: A64: add support for ld/st un


From: Peter Maydell
Subject: Re: [Qemu-devel] [PATCH 02/21] target-arm: A64: add support for ld/st unsigned imm
Date: Fri, 20 Dec 2013 16:08:10 +0000

On 19 December 2013 17:46, Richard Henderson <address@hidden> wrote:
> On 12/17/2013 07:12 AM, Peter Maydell wrote:
>> +        if (size == 3 && opc == 2) {
>> +            /* PRFM - prefetch */
>> +            return;
>> +        }
>> +        if (opc == 3 && size > 1) {
>> +            unallocated_encoding(s);
>> +            return;
>> +        }
>> +        is_store = (opc == 0);
>> +        is_signed = opc & (1<<1);
>> +        is_extended = (size < 3) && (opc & 1);
>
> I thought we'd discussed rearranging this bit of decoding to better match the
> ARM?

Can't find anything in my email archive but I wouldn't be surprised
if I was just searching on the wrong keywords...

> In particular, opc = 2 && size = 2 should be unallocated.

This is LDRSW (immediate), not unallocated, isn't it?

I agree the decode logic isn't laid out the same as the ARM ARM,
but I'm pretty sure it's correct.

> And please no (1<<1).

Agreed.

-- PMM



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