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[Qemu-devel] [PATCH 01/10] target-arm: A64: Add support for dumping AArc
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 01/10] target-arm: A64: Add support for dumping AArch64 VFP register state |
Date: |
Sat, 28 Dec 2013 21:49:02 +0000 |
From: Alexander Graf <address@hidden>
When dumping the current CPU state, we can also get a request
to dump the FPU state along with the CPU's integer state.
Add support to dump the VFP state when that flag is set, so that
we can properly debug code that modifies floating point registers.
Signed-off-by: Alexander Graf <address@hidden>
[WN: Commit message tweak, rebased. Output all registers, two per-line.]
Signed-off-by: Will Newton <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate-a64.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 40c6fc4..6f2b26e 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -119,6 +119,22 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
psr & PSTATE_C ? 'C' : '-',
psr & PSTATE_V ? 'V' : '-');
cpu_fprintf(f, "\n");
+
+ if (flags & CPU_DUMP_FPU) {
+ int numvfpregs = 32;
+ for (i = 0; i < numvfpregs; i += 2) {
+ uint64_t vlo = float64_val(env->vfp.regs[i * 2]);
+ uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]);
+ cpu_fprintf(f, "q%02d.0=%016" PRIx64 ":%016" PRIx64 " ",
+ i, vlo, vhi);
+ vlo = float64_val(env->vfp.regs[(i + 1) * 2]);
+ vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]);
+ cpu_fprintf(f, "q%02d.0=%016" PRIx64 ":%016" PRIx64 "\n",
+ i + 1, vlo, vhi);
+ }
+ cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n",
+ vfp_get_fpcr(env), vfp_get_fpsr(env));
+ }
}
static int get_mem_index(DisasContext *s)
--
1.8.5
- [Qemu-devel] [PATCH 00/10] A64 decoder patchset 5: most floating point, Peter Maydell, 2013/12/28
- [Qemu-devel] [PATCH 07/10] target-arm: A64: Add support for floating point compare, Peter Maydell, 2013/12/28
- [Qemu-devel] [PATCH 04/10] target-arm: A64: Add "Floating-point data-processing (2 source)" insns, Peter Maydell, 2013/12/28
- [Qemu-devel] [PATCH 06/10] target-arm: A64: Add fmov (scalar, immediate) instruction, Peter Maydell, 2013/12/28
- [Qemu-devel] [PATCH 01/10] target-arm: A64: Add support for dumping AArch64 VFP register state,
Peter Maydell <=
- [Qemu-devel] [PATCH 09/10] target-arm: A64: Add support for floating point cond select, Peter Maydell, 2013/12/28
- [Qemu-devel] [PATCH 08/10] target-arm: A64: Add support for floating point conditional compare, Peter Maydell, 2013/12/28
- [Qemu-devel] [PATCH 03/10] target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum, Peter Maydell, 2013/12/28
- [Qemu-devel] [PATCH 02/10] target-arm: A64: Fix vector register access on bigendian hosts, Peter Maydell, 2013/12/28