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[Qemu-devel] [PULL 47/52] target-arm: use c13_context field for CONTEXTI
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 47/52] target-arm: use c13_context field for CONTEXTIDR |
Date: |
Mon, 6 Jan 2014 11:30:52 +0000 |
From: Sergey Fedorov <address@hidden>
Use c13_context field instead of c13_fcse for CONTEXTIDR register
definition.
Signed-off-by: Sergey Fedorov <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 265675d..4af2f9c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -397,7 +397,7 @@ static const ARMCPRegInfo cp_reginfo[] = {
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
.resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
{ .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 =
1,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_context),
.resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write,
},
/* ??? This covers not just the impdef TLB lockdown registers but also
* some v7VMSA registers relating to TEX remap, so it is overly broad.
--
1.8.5
- [Qemu-devel] [PULL 48/52] target-arm: remove raw_read|write duplication, (continued)
- [Qemu-devel] [PULL 48/52] target-arm: remove raw_read|write duplication, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 50/52] target-arm: fix build with gcc 4.8.2, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 46/52] char/cadence_uart: Implement Tx flow control, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 43/52] char/cadence_uart: Fix can_receive logic, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 44/52] char/cadence_uart: Use the TX fifo for transmission, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 41/52] char/cadence_uart: Define Missing SR/ISR fields, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 40/52] char/cadence_uart: Simplify status generation, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 39/52] char/cadence_uart: s/r_fifo/rx_fifo, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 38/52] char/cadence_uart: Fix reset., Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 37/52] char/cadence_uart: Add missing uart_update_state, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 47/52] target-arm: use c13_context field for CONTEXTIDR,
Peter Maydell <=
- [Qemu-devel] [PULL 36/52] char/cadence_uart: Mark struct fields as public/private, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 35/52] target-arm: Give the FPSCR rounding modes names, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 34/52] target-arm: A64: Add support for floating point cond select, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 33/52] target-arm: A64: Add support for floating point conditional compare, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 45/52] char/cadence_uart: Delete redundant rx rst logic, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 31/52] target-arm: A64: Add fmov (scalar, immediate) instruction, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 42/52] char/cadence_uart: Remove TX timer & add TX FIFO state, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 30/52] target-arm: A64: Add "Floating-point data-processing (3 source)" insns, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 26/52] target-arm: A64: Add support for dumping AArch64 VFP register state, Peter Maydell, 2014/01/06
- [Qemu-devel] [PULL 28/52] target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum, Peter Maydell, 2014/01/06