[Qemu-devel] [V6 PATCH 18/18] target-ppc: Scalar Non-Signalling Conversions

[Tom Musta]

This patch adds the non-signalling scalar conversion instructions:

  - VSX Scalar Convert Single Precision to Double Precision
    Non-Signalling (xscvspdpn)
  - VSX Scalar Convert Double Precision to Single Precision
    Non-Signalling (xscvdpspn)

Signed-off-by: Tom Musta <address@hidden>
---
V6: New.

 target-ppc/fpu_helper.c |   19 +++++++++++++++++++
 target-ppc/helper.h     |    2 ++
 target-ppc/translate.c  |    4 ++++
 3 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index c1524e3..8bb647c 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2487,6 +2487,25 @@ VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, f32[j], 
f64[i], 1)
 VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, f64[i], f32[j], 0)
 VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, f32[j], f64[i], 0)
 
+#define VSX_CVT_FP_TO_FP_NONSIG(op, stp, ttp, sfld, tfld) \
+void helper_##op(CPUPPCState *env, uint32_t opcode)       \
+{                                                         \
+    ppc_vsr_t xt, xb;                                     \
+                                                          \
+    getVSR(xB(opcode), &xb, env);                         \
+    getVSR(xT(opcode), &xt, env);                         \
+                                                          \
+    float_status tstat = env->fp_status;                  \
+    set_float_exception_flags(0, &tstat);                 \
+                                                          \
+    xt.tfld[0] = stp##_to_##ttp(xb.sfld[0], &tstat);      \
+                                                          \
+    putVSR(xT(opcode), &xt, env);                         \
+}
+
+VSX_CVT_FP_TO_FP_NONSIG(xscvdpspn, float64, float32, f64, f32)
+VSX_CVT_FP_TO_FP_NONSIG(xscvspdpn, float32, float64, f32, f64)
+
 /* VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
  *   op    - instruction mnemonic
  *   nels  - number of elements (1, 2 or 4)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 300e194..753ab01 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -273,7 +273,9 @@ DEF_HELPER_2(xscmpudp, void, env, i32)
 DEF_HELPER_2(xsmaxdp, void, env, i32)
 DEF_HELPER_2(xsmindp, void, env, i32)
 DEF_HELPER_2(xscvdpsp, void, env, i32)
+DEF_HELPER_2(xscvdpspn, void, env, i32)
 DEF_HELPER_2(xscvspdp, void, env, i32)
+DEF_HELPER_2(xscvspdpn, void, env, i32)
 DEF_HELPER_2(xscvdpsxds, void, env, i32)
 DEF_HELPER_2(xscvdpsxws, void, env, i32)
 DEF_HELPER_2(xscvdpuxds, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 48b93c8..dde5a06 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7408,7 +7408,9 @@ GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
@@ -10246,7 +10248,9 @@ GEN_XX2FORM(xscmpudp,  0x0C, 0x04, PPC2_VSX),
 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
+GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
+GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
-- 
1.7.1