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[Qemu-devel] [PATCH 14/24] target-arm: Implement AArch64 dummy MDSCR_EL1
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 14/24] target-arm: Implement AArch64 dummy MDSCR_EL1 |
Date: |
Tue, 21 Jan 2014 20:12:20 +0000 |
We don't support letting the guest do debug, but Linux prods the
monitor debug system control register anyway, so implement a dummy
RAZ/WI version.
---
target-arm/helper.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ffe245f..69cce6f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1761,6 +1761,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 7,
.access = PL1_W, .type = ARM_CP_NO_MIGRATE,
.writefn = tlbi_aa64_vaa_write },
+ /* Dummy implementation of monitor debug system control register:
+ * we don't support debug.
+ */
+ { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
REGINFO_SENTINEL
};
--
1.8.5
- [Qemu-devel] [PATCH 17/24] target-arm: Implement AArch64 TCR_EL1, (continued)
[Qemu-devel] [PATCH 21/24] target-arm: Implement AArch64 generic timers, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 14/24] target-arm: Implement AArch64 dummy MDSCR_EL1,
Peter Maydell <=
[Qemu-devel] [PATCH 07/24] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 15/24] target-arm: Implement AArch64 memory attribute registers, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 05/24] target-arm: Add exception level to the AArch64 TB flags, Peter Maydell, 2014/01/21