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Re: [Qemu-devel] [PATCH 00/21] A64: Add Neon instructions, second and th
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 00/21] A64: Add Neon instructions, second and third sets |
Date: |
Sun, 26 Jan 2014 19:33:07 +0000 |
On 26 January 2014 19:24, Peter Maydell <address@hidden> wrote:
> This patch series is kind of in two parts. The first 8 patches
> are the "Neon second set" that's already been pretty much reviewed;
> I'm resending them just because there were a few minor nits that
> came up in the last round which have been fixed:
> * patch 6 added the missing SQDMULH/SQRDMULH unallocated/unimplemented
> case in the SIMD 3-same initial decode
> * patch 7 now uses the _i32 vector element accessors
> * patch 8 fixed a few codestyle nits
> (RTH: these all seemed trivial enough that I've left your
> reviewed-by tags in place).
>
> Patches 9..21 are new, and fill in a number of gaps that bring
> us up to (and past) parity with the SuSE tree for coverage:
> * more SIMD 3-same ops, including basically all the integer ones
> * the "scalar pairwise" instruction group
> * more SIMD scalar-3-same ops, including all the integer ones
> * some (but not all) of the 2-reg misc and scalar 2-reg misc groups
> (by the same rationale as with 3-same, we aim for "anything
> implemented in the SuSE tree" plus enough to make it reasonably
> likely we've got the general function structure correct)
I forgot to mention, but you can find a git tree with these in at
git://git.linaro.org/people/peter.maydell/qemu-arm.git a64-neon
thanks
-- PMM
- [Qemu-devel] [PATCH 09/21] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns, (continued)
- [Qemu-devel] [PATCH 09/21] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 06/21] target-arm: A64: Add integer ops from SIMD 3-same group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 08/21] target-arm: A64: Add SIMD shift by immediate, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 12/21] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 15/21] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 13/21] target-arm: A64: Implement scalar pairwise ops, Peter Maydell, 2014/01/26
- Re: [Qemu-devel] [PATCH 00/21] A64: Add Neon instructions, second and third sets,
Peter Maydell <=
- [Qemu-devel] [PATCH 16/21] target-arm: A64: Add skeleton decode for SIMD 2-reg misc group, Peter Maydell, 2014/01/26