[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 07/24] target-arm: A64: Make cache ID registers
|
From: |
Peter Maydell |
|
Subject: |
Re: [Qemu-devel] [PATCH 07/24] target-arm: A64: Make cache ID registers visible to AArch64 |
|
Date: |
Tue, 28 Jan 2014 08:45:30 +0000 |
On 28 January 2014 01:46, Peter Crosthwaite
<address@hidden> wrote:
> There seem to be multiple instances in this series where you fallback
> to open coded R/W accessor functions for the sake of access checks. Is
> it better to define a bool check_access() fn hook in ARMCPRegInfo and
> leave the actual write/read behaviour to the data driven mechanisms?
> This may also minimise the need for raw_write hook usages as it serves
> to isolate the actual state change into its own self contained
> definition (whether open coded or not).
Yes, I think it's probably going to be better to do that. We may need
to make it more than just bool, though since for AArch64 the
kind of exception can be different I think -- the specific syndrome
information can vary.
thanks
-- PMM
- [Qemu-devel] [PATCH 19/24] target-arm: Implement AArch64 TTBR*, (continued)
[Qemu-devel] [PATCH 21/24] target-arm: Implement AArch64 generic timers, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 14/24] target-arm: Implement AArch64 dummy MDSCR_EL1, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 07/24] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 15/24] target-arm: Implement AArch64 memory attribute registers, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 05/24] target-arm: Add exception level to the AArch64 TB flags, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 01/24] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs, Peter Maydell, 2014/01/21