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Re: [Qemu-devel] [PATCH 10/21] target-arm: A64: Implement remaining non-
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 10/21] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns |
Date: |
Tue, 28 Jan 2014 09:13:35 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.2.0 |
On 01/26/2014 11:25 AM, Peter Maydell wrote:
> @@ -6773,9 +6801,9 @@ static void disas_simd_3same_int(DisasContext *s,
> uint32_t insn)
> case 0x8: /* SSHL, USHL */
> {
> static NeonGenTwoOpFn * const fns[3][2] = {
> - { gen_helper_neon_shl_u8, gen_helper_neon_shl_s8 },
> - { gen_helper_neon_shl_u16, gen_helper_neon_shl_s16 },
> - { gen_helper_neon_shl_u32, gen_helper_neon_shl_s32 },
> + { gen_helper_neon_shl_s8, gen_helper_neon_shl_u8 },
> + { gen_helper_neon_shl_s16, gen_helper_neon_shl_u16 },
> + { gen_helper_neon_shl_s32, gen_helper_neon_shl_u32 },
> };
> genfn = fns[size][u];
> break;
Oops, I clearly missed this in the review of the previous patch.
But these bug fixes ought to be folded into the previous.
Otherwise,
Reviewed-by: Richard Henderson <address@hidden>
> + case 0xd: /* SMIN, UMIN */
> + {
> + static NeonGenTwoOpFn * const fns[3][2] = {
> + { gen_helper_neon_min_s8, gen_helper_neon_min_u8 },
> + { gen_helper_neon_min_s16, gen_helper_neon_min_u16 },
> + { gen_helper_neon_min_s32, gen_helper_neon_min_u32 },
> + };
> + genfn = fns[size][u];
> + break;
Out of curiosity, what logic are you applying to using the neon helper
functions and implementing stuff inline?
It appears that you're implementing all of the 64-bit stuff inline, but using
the existing 32-bit helpers, even if the helpers are remarkably small, like
some of these.
r~
- [Qemu-devel] [PATCH 00/21] A64: Add Neon instructions, second and third sets, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 20/21] target-arm: A64: Add 2-reg-misc REV* instructions, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 19/21] target-arm: A64: Add narrowing 2-reg-misc instructions, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 17/21] target-arm: A64: Implement 2-register misc compares, ABS, NEG, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 18/21] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 10/21] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns, Peter Maydell, 2014/01/26
- Re: [Qemu-devel] [PATCH 10/21] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns,
Richard Henderson <=
- [Qemu-devel] [PATCH 01/21] target-arm: A64: Add SIMD three-different multiply accumulate insns, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 21/21] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 11/21] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 02/21] target-arm: A64: Add SIMD three-different ABDL instructions, Peter Maydell, 2014/01/26
- [Qemu-devel] [PATCH 05/21] target-arm: A64: Add logic ops from SIMD 3 same group, Peter Maydell, 2014/01/26