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Re: [Qemu-devel] [PATCH 07/24] target-arm: A64: Make cache ID registers
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 07/24] target-arm: A64: Make cache ID registers visible to AArch64 |
Date: |
Tue, 28 Jan 2014 18:16:47 +0000 |
On 28 January 2014 18:12, Peter Maydell <address@hidden> wrote:
> typedef enum CPAccessResult {
> /* Access is permitted */
> CP_ACCESS_OK = 0,
> /* Access fails due to a configurable trap or enable which would
> * result in an exception syndrome other than 'uncategorized'
> */
> CP_ACCESS_TRAP = 1,
> /* Access fails and should result in an exception syndrome of
> * 'uncategorized'
> */
> CP_ACCESS_TRAP = 2,
> } CPAccessResult;
The =2 case should be some other name, of course. I'd rather
not use the obvious "CP_ACCESS_UNCATEGORIZED" because that
implies "use this if you don't know", when actually the set of
things which cause Uncategorized exceptions is a specific list,
and it's the 'due to a configurable trap' case which is defined
as "all those which aren't defined to cause an Uncategorized
exception". On the other hand I can't come up with a better
name right now...
thanks
-- PMM
[Qemu-devel] [PATCH 21/24] target-arm: Implement AArch64 generic timers, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 14/24] target-arm: Implement AArch64 dummy MDSCR_EL1, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 07/24] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 15/24] target-arm: Implement AArch64 memory attribute registers, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 05/24] target-arm: Add exception level to the AArch64 TB flags, Peter Maydell, 2014/01/21
[Qemu-devel] [PATCH 01/24] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs, Peter Maydell, 2014/01/21