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[Qemu-devel] [PATCH v2 06/35] target-arm: Log bad system register access
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 06/35] target-arm: Log bad system register accesses with LOG_UNIMP |
Date: |
Fri, 31 Jan 2014 15:45:14 +0000 |
Log guest attempts to access unimplemented system registers via
the LOG_UNIMP reporting mechanism (for both the 32 bit and 64 bit
instruction sets). This is particularly useful for debugging
problems where the guest is trying to use a system register that
QEMU doesn't implement.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/translate-a64.c | 7 ++++++-
target-arm/translate.c | 13 +++++++++++++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index ee768f2..f808998 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1172,7 +1172,12 @@ static void handle_sys(DisasContext *s, uint32_t insn,
bool isread,
crn, crm, op0, op1, op2));
if (!ri) {
- /* Unknown register */
+ /* Unknown register; this might be a guest error or a QEMU
+ * unimplemented feature.
+ */
+ qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 "
+ "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
+ isread ? "read" : "write", op0, op1, crn, crm, op2);
unallocated_encoding(s);
return;
}
diff --git a/target-arm/translate.c b/target-arm/translate.c
index e701c0f..45886f9 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6923,6 +6923,19 @@ static int disas_coproc_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
return 0;
}
+ /* Unknown register; this might be a guest error or a QEMU
+ * unimplemented feature.
+ */
+ if (is64) {
+ qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
+ "64 bit system register cp:%d opc1: %d crm:%d\n",
+ isread ? "read" : "write", cpnum, opc1, crm);
+ } else {
+ qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch32 "
+ "system register cp:%d opc1:%d crn:%d crm:%d opc2:%d\n",
+ isread ? "read" : "write", cpnum, opc1, crn, crm, opc2);
+ }
+
return 1;
}
--
1.8.5
- [Qemu-devel] [PATCH v2 24/35] target-arm: Implement AArch64 TLB invalidate ops, (continued)
- [Qemu-devel] [PATCH v2 24/35] target-arm: Implement AArch64 TLB invalidate ops, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 05/35] target-arm: Remove unused ARMCPUState sr substruct, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 14/35] target-arm: Convert miscellaneous reginfo structs to accessfn, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 31/35] target-arm: Implement AArch64 MPIDR, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 27/35] target-arm: Implement AArch64 SCTLR_EL1, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 12/35] target-arm: Convert performance monitor reginfo to accesfn, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 33/35] target-arm: Implement AArch64 ID and feature registers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 13/35] target-arm: Convert generic timer reginfo to accessfn, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 16/35] target-arm: Remove unnecessary code now read/write fns can't fail, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 20/35] target-arm: Implement AArch64 CurrentEL sysreg, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 06/35] target-arm: Log bad system register accesses with LOG_UNIMP,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 29/35] target-arm: Implement AArch64 VBAR_EL1, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 18/35] target-arm: Fix incorrect type for value argument to write_raw_cp_reg, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 19/35] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 17/35] target-arm: Remove failure status return from read/write_raw_cp_reg, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 04/35] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 26/35] target-arm: Implement AArch64 memory attribute registers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 09/35] target-arm: A64: Implement MSR (immediate) instructions, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 02/35] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 34/35] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 15/35] target-arm: Drop success/fail return from cpreg read and write functions, Peter Maydell, 2014/01/31