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[Qemu-devel] [PATCH v2 17/35] target-arm: Remove failure status return f
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 17/35] target-arm: Remove failure status return from read/write_raw_cp_reg |
Date: |
Fri, 31 Jan 2014 15:45:25 +0000 |
The read_raw_cp_reg and write_raw_cp_reg functions can now never
fail (in fact they should never have failed previously unless
there was a bug in a reginfo that meant no raw accessor was
provided for a might-trap register). This allows us to clean up
their prototypes so the write function returns void and the
read function returns the value read, which in turn lets us
simplify the callers.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 36 ++++++++++++------------------------
1 file changed, 12 insertions(+), 24 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 10aeccc..577b060 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -126,35 +126,30 @@ static void raw_write(CPUARMState *env, const
ARMCPRegInfo *ri,
}
}
-static bool read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t *v)
+static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
{
- /* Raw read of a coprocessor register (as needed for migration, etc)
- * return true on success, false if the read is impossible for some reason.
- */
+ /* Raw read of a coprocessor register (as needed for migration, etc). */
if (ri->type & ARM_CP_CONST) {
- *v = ri->resetvalue;
+ return ri->resetvalue;
} else if (ri->raw_readfn) {
- *v = ri->raw_readfn(env, ri);
+ return ri->raw_readfn(env, ri);
} else if (ri->readfn) {
- *v = ri->readfn(env, ri);
+ return ri->readfn(env, ri);
} else {
- *v = raw_read(env, ri);
+ return raw_read(env, ri);
}
- return true;
}
-static bool write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
+static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
int64_t v)
{
/* Raw write of a coprocessor register (as needed for migration, etc).
- * Return true on success, false if the write is impossible for some
reason.
* Note that constant registers are treated as write-ignored; the
* caller should check for success by whether a readback gives the
* value written.
*/
if (ri->type & ARM_CP_CONST) {
- return true;
+ return;
} else if (ri->raw_writefn) {
ri->raw_writefn(env, ri, v);
} else if (ri->writefn) {
@@ -162,7 +157,6 @@ static bool write_raw_cp_reg(CPUARMState *env, const
ARMCPRegInfo *ri,
} else {
raw_write(env, ri, v);
}
- return true;
}
bool write_cpustate_to_list(ARMCPU *cpu)
@@ -174,7 +168,7 @@ bool write_cpustate_to_list(ARMCPU *cpu)
for (i = 0; i < cpu->cpreg_array_len; i++) {
uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
const ARMCPRegInfo *ri;
- uint64_t v;
+
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
if (!ri) {
ok = false;
@@ -183,11 +177,7 @@ bool write_cpustate_to_list(ARMCPU *cpu)
if (ri->type & ARM_CP_NO_MIGRATE) {
continue;
}
- if (!read_raw_cp_reg(&cpu->env, ri, &v)) {
- ok = false;
- continue;
- }
- cpu->cpreg_values[i] = v;
+ cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
}
return ok;
}
@@ -200,7 +190,6 @@ bool write_list_to_cpustate(ARMCPU *cpu)
for (i = 0; i < cpu->cpreg_array_len; i++) {
uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
uint64_t v = cpu->cpreg_values[i];
- uint64_t readback;
const ARMCPRegInfo *ri;
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
@@ -215,9 +204,8 @@ bool write_list_to_cpustate(ARMCPU *cpu)
* (to catch read-only registers and partially read-only
* registers where the incoming migration value doesn't match)
*/
- if (!write_raw_cp_reg(&cpu->env, ri, v) ||
- !read_raw_cp_reg(&cpu->env, ri, &readback) ||
- readback != v) {
+ write_raw_cp_reg(&cpu->env, ri, v);
+ if (read_raw_cp_reg(&cpu->env, ri) != v) {
ok = false;
}
}
--
1.8.5
- [Qemu-devel] [PATCH v2 27/35] target-arm: Implement AArch64 SCTLR_EL1, (continued)
- [Qemu-devel] [PATCH v2 27/35] target-arm: Implement AArch64 SCTLR_EL1, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 12/35] target-arm: Convert performance monitor reginfo to accesfn, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 33/35] target-arm: Implement AArch64 ID and feature registers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 13/35] target-arm: Convert generic timer reginfo to accessfn, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 16/35] target-arm: Remove unnecessary code now read/write fns can't fail, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 20/35] target-arm: Implement AArch64 CurrentEL sysreg, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 06/35] target-arm: Log bad system register accesses with LOG_UNIMP, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 29/35] target-arm: Implement AArch64 VBAR_EL1, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 18/35] target-arm: Fix incorrect type for value argument to write_raw_cp_reg, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 19/35] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 17/35] target-arm: Remove failure status return from read/write_raw_cp_reg,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 04/35] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 26/35] target-arm: Implement AArch64 memory attribute registers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 09/35] target-arm: A64: Implement MSR (immediate) instructions, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 02/35] target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 34/35] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 15/35] target-arm: Drop success/fail return from cpreg read and write functions, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 32/35] target-arm: Implement AArch64 generic timers, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 35/35] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI, Peter Maydell, 2014/01/31
- [Qemu-devel] [PATCH v2 01/35] target-arm: Fix raw read and write functions on AArch64 registers, Peter Maydell, 2014/01/31