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[Qemu-devel] [PATCH v2 04/13] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_P
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 04/13] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR |
Date: |
Sat, 1 Feb 2014 22:59:58 +0000 |
We have macros for marking TCGv values as unused, checking if they
are unused and comparing them to each other. However these only exist
for TCGv_i32 and TCGv_i64; add them for TCGv_ptr as well.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
tcg/tcg.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index c72af6c..f7efcb4 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -324,13 +324,16 @@ typedef int TCGv_i64;
#define TCGV_EQUAL_I32(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b))
#define TCGV_EQUAL_I64(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b))
+#define TCGV_EQUAL_PTR(a, b) (GET_TCGV_PTR(a) == GET_TCGV_PTR(b))
/* Dummy definition to avoid compiler warnings. */
#define TCGV_UNUSED_I32(x) x = MAKE_TCGV_I32(-1)
#define TCGV_UNUSED_I64(x) x = MAKE_TCGV_I64(-1)
+#define TCGV_UNUSED_PTR(x) x = MAKE_TCGV_PTR(-1)
#define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) == -1)
#define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) == -1)
+#define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) == -1)
/* call flags */
/* Helper does not read globals (either directly or through an exception). It
--
1.8.5
- [Qemu-devel] [PATCH v2 10/13] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT, (continued)
- [Qemu-devel] [PATCH v2 10/13] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT, Peter Maydell, 2014/02/01
- [Qemu-devel] [PATCH v2 13/13] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group, Peter Maydell, 2014/02/01
- [Qemu-devel] [PATCH v2 03/13] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD, Peter Maydell, 2014/02/01
- [Qemu-devel] [PATCH v2 02/13] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns, Peter Maydell, 2014/02/01
- [Qemu-devel] [PATCH v2 05/13] target-arm: A64: Implement scalar pairwise ops, Peter Maydell, 2014/02/01
- [Qemu-devel] [PATCH v2 09/13] target-arm: A64: Implement 2-register misc compares, ABS, NEG, Peter Maydell, 2014/02/01
- [Qemu-devel] [PATCH v2 07/13] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc, Peter Maydell, 2014/02/01
- [Qemu-devel] [PATCH v2 12/13] target-arm: A64: Add 2-reg-misc REV* instructions, Peter Maydell, 2014/02/01
- [Qemu-devel] [PATCH v2 04/13] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 06/13] target-arm: A64: Implement remaining integer scalar-3-same insns, Peter Maydell, 2014/02/01
- [Qemu-devel] [PATCH v2 11/13] target-arm: A64: Add narrowing 2-reg-misc instructions, Peter Maydell, 2014/02/01
- [Qemu-devel] [PATCH v2 01/13] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns, Peter Maydell, 2014/02/01
- [Qemu-devel] [PATCH v2 08/13] target-arm: A64: Add skeleton decode for SIMD 2-reg misc group, Peter Maydell, 2014/02/01
- Re: [Qemu-devel] [PATCH v2 00/13] A64: Add Neon instructions, third set, Peter Maydell, 2014/02/03