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[Qemu-devel] [PATCH 1/6] target-arm: A64: Add opcode comments to disas_s
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 1/6] target-arm: A64: Add opcode comments to disas_simd_three_reg_diff |
Date: |
Sun, 16 Feb 2014 18:21:06 +0000 |
The opcode switch in disas_simd_three_reg_diff() is missing the
customary comments indicating which cases correspond to which
instructions. Add them.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate-a64.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 3de9cad..d4e7a20 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -7091,24 +7091,24 @@ static void disas_simd_three_reg_diff(DisasContext *s,
uint32_t insn)
/* 128 x 128 -> 64 */
unsupported_encoding(s, insn);
break;
- case 9:
- case 11:
- case 13:
- case 14:
+ case 9: /* SQDMLAL, SQDMLAL2 */
+ case 11: /* SQDMLSL, SQDMLSL2 */
+ case 13: /* SQDMULL, SQDMULL2 */
+ case 14: /* PMULL, PMULL2 */
if (is_u) {
unallocated_encoding(s);
return;
}
/* fall through */
- case 0:
- case 2:
+ case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
+ case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
unsupported_encoding(s, insn);
break;
- case 5:
- case 7:
- case 8:
- case 10:
- case 12:
+ case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
+ case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
+ case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
+ case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
+ case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
/* 64 x 64 -> 128 */
if (size == 3) {
unallocated_encoding(s);
--
1.8.5
- [Qemu-devel] [PATCH 0/6] A64: finish Neon 3-reg-diff category, add LDTR/STTR, Peter Maydell, 2014/02/16
- [Qemu-devel] [PATCH 1/6] target-arm: A64: Add opcode comments to disas_simd_three_reg_diff,
Peter Maydell <=
- [Qemu-devel] [PATCH 5/6] target-arm: A64: Implement PMULL instruction, Peter Maydell, 2014/02/16
- [Qemu-devel] [PATCH 4/6] target-arm: A64: Implement narrowing three-reg-diff operations, Peter Maydell, 2014/02/16
- [Qemu-devel] [PATCH 3/6] target-arm: A64: Implement the wide 3-reg-different operations, Peter Maydell, 2014/02/16
- [Qemu-devel] [PATCH 6/6] target-arm: A64: Implement unprivileged load/store, Peter Maydell, 2014/02/16
- [Qemu-devel] [PATCH 2/6] target-arm: A64: Add most remaining three-reg-diff widening ops, Peter Maydell, 2014/02/16
- Re: [Qemu-devel] [PATCH 0/6] A64: finish Neon 3-reg-diff category, add LDTR/STTR, Richard Henderson, 2014/02/17