It's been a little while since I looked, however this was my interpretation
of the table 3-12 on p.66 of the SBus specification. While that particular
table refers to the acknowledgment cycle from the slave back to the master,
it seems to work here in the same way when transferring between the master
and the slave.
It's not that I think your comment is wrong about how SBus does
byte transfers, or that the code is wrong, I just don't think that the
reason for the code is the SBus behaviour; it's the device behaviour.
QEMU abstracts a bus's mechanisms for transferring data into the
MemoryRegion ops, which means that for a byte access you'll
always get called with the byte value in the low 8 bits of the input
argument. This would be true whether SBus passed byte values in
lines 31..28, 7..0 or by sending them one bit at a time on D13. The
relation between a byte write and a word write here is a property
of the device, not the bus.
(You'll notice that 3-12 allows the slave to send the byte data
in various different lanes depending on which size acknowlegement
it chooses to send. The documentation of what the master does
is on page 53 and actually says you have to send it in two lanes
for a non-aligned address, and certainly QEMU won't do anything
corresponding to that. In any case I don't think it's relevant here.)