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[Qemu-devel] [PATCH] hw/intc/arm_gic: Fix GIC_SET_LEVEL
From: |
Christoffer Dall |
Subject: |
[Qemu-devel] [PATCH] hw/intc/arm_gic: Fix GIC_SET_LEVEL |
Date: |
Fri, 21 Feb 2014 17:03:50 -0800 |
The GIC_SET_LEVEL macro unfortunately overwrote the entire level
bitmask instead of just or'ing on the necessary bits, causing active
level PPIs on a core to clear PPIs on other cores.
I introduced this bug, sorry about that.
Reported-by: Rob Herring <address@hidden>
Signed-off-by: Christoffer Dall <address@hidden>
---
hw/intc/gic_internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index 92a6f7a..48a58d7 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -40,7 +40,7 @@
#define GIC_SET_MODEL(irq) s->irq_state[irq].model = true
#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = false
#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
-#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
+#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level |= (cm)
#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
#define GIC_SET_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger = true
--
1.8.5.2
- [Qemu-devel] [PATCH] hw/intc/arm_gic: Fix GIC_SET_LEVEL,
Christoffer Dall <=