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Re: [Qemu-devel] [PATCH v3 23/31] target-arm: Implement AArch64 view of
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH v3 23/31] target-arm: Implement AArch64 view of CPACR |
Date: |
Tue, 25 Feb 2014 18:34:09 +1000 |
On Sun, Feb 16, 2014 at 2:07 AM, Peter Maydell <address@hidden> wrote:
> Implement the AArch64 view of the CPACR. The AArch64
> CPACR is defined to have a lot of RES0 bits, but since
> the architecture defines that RES0 bits may be implemented
> as reads-as-written and we know that a v8 CPU will have
> no registered coprocessors for cp0..cp13 we can safely
> implement the whole register this way.
>
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
> ---
> target-arm/cpu.h | 2 +-
> target-arm/helper.c | 3 ++-
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 571b033..1f6f65d 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -172,7 +172,7 @@ typedef struct CPUARMState {
> uint32_t c0_cpuid;
> uint64_t c0_cssel; /* Cache size selection. */
> uint64_t c1_sys; /* System control register. */
> - uint32_t c1_coproc; /* Coprocessor access register. */
> + uint64_t c1_coproc; /* Coprocessor access register. */
> uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
> uint32_t c1_scr; /* secure config register. */
> uint64_t ttbr0_el1; /* MMU translation table base 0. */
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index c50ca5a..d35cc73 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -458,7 +458,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
> */
> { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
> .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
> - { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
> + { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
> + .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
> .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
> .resetvalue = 0, .writefn = cpacr_write },
> REGINFO_SENTINEL
> --
> 1.8.5
>
>
- [Qemu-devel] [PATCH v3 10/31] target-arm: Implement AArch64 TCR_EL1, (continued)
- [Qemu-devel] [PATCH v3 10/31] target-arm: Implement AArch64 TCR_EL1, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 12/31] target-arm: Implement AArch64 TTBR*, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 01/31] target-arm: Fix raw read and write functions on AArch64 registers, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 17/31] target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 24/31] target-arm: Add utility function for checking AA32/64 state of an EL, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 23/31] target-arm: Implement AArch64 view of CPACR, Peter Maydell, 2014/02/15
- Re: [Qemu-devel] [PATCH v3 23/31] target-arm: Implement AArch64 view of CPACR,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH v3 22/31] target-arm: A64: Implement MSR (immediate) instructions, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 16/31] target-arm: Implement AArch64 dummy breakpoint and watchpoint registers, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 30/31] target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 28/31] target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 05/31] target-arm: Implement AArch64 cache invalidate/clean ops, Peter Maydell, 2014/02/15
- [Qemu-devel] [PATCH v3 31/31] target-arm: Add v8 mmu translation support, Peter Maydell, 2014/02/15