[Qemu-devel] [PATCH v5] target-sparc: Add and use CPU_FEATURE_CASA

[Sebastian Huber]

The LEON3 processor has support for the CASA instruction which is
normally only available for SPARC V9 processors. Binutils 2.24
and GCC 4.9 will support this instruction for LEON3. GCC uses it to
generate C11 atomic operations.

The CAS synthetic instruction uses an ASI of 0x80. If TARGET_SPARC64 is
not defined use a supervisor data load/store for an ASI of 0x80 in
helper_ld_asi()/helper_st_asi(). The supervisor data load/store was
choosen according to the LEON3 documentation.

The ASI 0x80 is defined in the SPARC V9 manual, Table 12—Address Space
Identifiers (ASIs). Here we have: 0x80, ASI_PRIMARY, Unrestricted
access, Primary address space.

Tested with the following program:

#include <assert.h>
#include <stdatomic.h>

void test(void)
{
atomic_int a;
int e;
_Bool b;

atomic_store(&a, 1);
e = 1;
b = atomic_compare_exchange_strong(&a, &e, 2);
assert(b);
assert(atomic_load(&a) == 2);

atomic_store(&a, 3);
e = 4;
b = atomic_compare_exchange_strong(&a, &e, 5);
assert(!b);
assert(atomic_load(&a) == 3);
}

Tested also on a NGMP board with a LEON4 processor.

Reviewed-by: Fabien Chouteau <address@hidden>
Reviewed-by: Andreas Färber <address@hidden>
Signed-off-by: Sebastian Huber <address@hidden>

v4: Fix coding style.

v5: Fix two typos. Generate an IU instead of FPU exception in case CASA 
is not supported by the CPU. Define CASA feature for all SPARC64 CPUs 
(due to the #ifndef TARGET_SPARC64 it must go into the #else branch).

--
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax     : +49 89 189 47 41-09
E-Mail  : address@hidden
PGP     : Public key available on request.

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0001-target-sparc-Add-and-use-CPU_FEATURE_CASA.patch
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