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[Qemu-devel] [PULL 12/14] tcg-aarch64: Support muluh, mulsh
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 12/14] tcg-aarch64: Support muluh, mulsh |
Date: |
Fri, 14 Mar 2014 13:09:49 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Claudio Fontana <address@hidden>
Tested-by: Claudio Fontana <address@hidden>
---
tcg/aarch64/tcg-target.c | 12 ++++++++++++
tcg/aarch64/tcg-target.h | 4 ++--
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index b9dc6bb..9c50820 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -311,6 +311,8 @@ typedef enum {
I3508_LSRV = 0x1ac02400,
I3508_ASRV = 0x1ac02800,
I3508_RORV = 0x1ac02c00,
+ I3508_SMULH = 0x9b407c00,
+ I3508_UMULH = 0x9bc07c00,
/* Logical shifted register instructions (without a shift). */
I3510_AND = 0x0a000000,
@@ -1565,6 +1567,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
args[5], const_args[4], const_args[5], true);
break;
+ case INDEX_op_muluh_i64:
+ tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2);
+ break;
+ case INDEX_op_mulsh_i64:
+ tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
+ break;
+
case INDEX_op_mov_i64:
case INDEX_op_mov_i32:
case INDEX_op_movi_i64:
@@ -1694,6 +1703,9 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } },
{ INDEX_op_sub2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },
+ { INDEX_op_muluh_i64, { "r", "r", "r" } },
+ { INDEX_op_mulsh_i64, { "r", "r", "r" } },
+
{ -1 },
};
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index f174ebd..c819095 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -89,8 +89,8 @@ typedef enum {
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
-#define TCG_TARGET_HAS_muluh_i64 0
-#define TCG_TARGET_HAS_mulsh_i64 0
+#define TCG_TARGET_HAS_muluh_i64 1
+#define TCG_TARGET_HAS_mulsh_i64 1
enum {
TCG_AREG0 = TCG_REG_X19,
--
1.8.5.3
- [Qemu-devel] [PULL 02/14] tcg-aarch64: Convert shift insns to tcg_out_insn, (continued)
- [Qemu-devel] [PULL 02/14] tcg-aarch64: Convert shift insns to tcg_out_insn, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 04/14] tcg-aarch64: Implement mov with tcg_out_insn, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 03/14] tcg-aarch64: Introduce tcg_out_insn_3401, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 05/14] tcg-aarch64: Handle constant operands to add, sub, and compare, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 06/14] tcg-aarch64: Handle constant operands to and, or, xor, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 07/14] tcg-aarch64: Support andc, orc, eqv, not, neg, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 08/14] tcg-aarch64: Support movcond, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 09/14] tcg-aarch64: Use tcg_out_insn for setcond, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 10/14] tcg-aarch64: Support deposit, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 11/14] tcg-aarch64: Support add2, sub2, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 12/14] tcg-aarch64: Support muluh, mulsh,
Richard Henderson <=
- [Qemu-devel] [PULL 13/14] tcg-aarch64: Support div, rem, Richard Henderson, 2014/03/14
- [Qemu-devel] [PULL 14/14] tcg-aarch64: Introduce tcg_out_insn_3405, Richard Henderson, 2014/03/14
- Re: [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2, Peter Maydell, 2014/03/15