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[Qemu-devel] [PULL 4/6] pl011: fix incorrect logic to set the RXFF flag
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 4/6] pl011: fix incorrect logic to set the RXFF flag |
Date: |
Wed, 19 Mar 2014 12:05:44 +0000 |
From: Rob Herring <address@hidden>
The receive fifo full bit should be set when 1 character is received and
the fifo is disabled or when 16 characters are in the fifo.
Signed-off-by: Rob Herring <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/char/pl011.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index 11c3a75..644aad7 100644
--- a/hw/char/pl011.c
+++ b/hw/char/pl011.c
@@ -221,7 +221,7 @@ static void pl011_put_fifo(void *opaque, uint32_t value)
s->read_fifo[slot] = value;
s->read_count++;
s->flags &= ~PL011_FLAG_RXFE;
- if (s->cr & 0x10 || s->read_count == 16) {
+ if (!(s->lcr & 0x10) || s->read_count == 16) {
s->flags |= PL011_FLAG_RXFF;
}
if (s->read_count == s->read_trigger) {
--
1.9.0
- [Qemu-devel] [PULL 0/6] target-arm queue, Peter Maydell, 2014/03/19
- [Qemu-devel] [PULL 6/6] target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD), Peter Maydell, 2014/03/19
- [Qemu-devel] [PULL 3/6] pl011: fix UARTRSR accesses corrupting the UARTCR value, Peter Maydell, 2014/03/19
- [Qemu-devel] [PULL 4/6] pl011: fix incorrect logic to set the RXFF flag,
Peter Maydell <=
- [Qemu-devel] [PULL 2/6] pl011: reset the fifo when enabled or disabled, Peter Maydell, 2014/03/19
- [Qemu-devel] [PULL 5/6] target-arm: A64: Add saturating int ops (SQNEG/SQABS), Peter Maydell, 2014/03/19
- [Qemu-devel] [PULL 1/6] ahci: fix sysbus support, Peter Maydell, 2014/03/19
- Re: [Qemu-devel] [PULL 0/6] target-arm queue, Peter Maydell, 2014/03/19