Re: [Qemu-devel] target-ppc: Problem with mtmsr emulation

[Alexander Graf]

> Am 28.03.2014 um 16:16 schrieb Thomas Huth <address@hidden>:
> 
> 
> Hi all!
> 
> There seems to be a problem with the emulation of the mtmsr instruction:
> According to the PowerISA spec, chapter Book III-S, the mtmsr opcode
> has a so-called "L" field at bit position 15. Looking at the function
> gen_mtmsr() in target-ppc/translate.c, the bit is taken into account
> since the function checks for ctx->opcode & 0x00010000.
> However, when looking at the GEN_HANDLER definition later in that file:
> 
> GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
> 
> you can see that the bit is marked as invalid bit in the 0x001FF801
> mask, thus if the bit is set, a program exception is generated instead
> of executing the gen_mtmsr() function.
> 
> An easy way to fix this for Book III-S is to change the mask to
> 0x001EF801 (just like the mask for mtmsrd), but I am afraid that this
> would break the Book III-E variant of mtmsr, since the embedded version
> does not have this bit defined. Any suggestions how to fix this problem
> in a proper way?

Please check in the older isa versions whether that bit is declared reserved.

If it is, we need to make sure we only match it on newer ISA conformance. In 
general there are 2 ways to do this:

  1) disjunct feature bits
  2) manual check inside the translating function

We don't have any way to manually apply logic like "match if bit x is not 
present" or have duplicate entries with manual ordering. I remember that I 
manually created a runtime computed not-bit a while ago for something, but I 
can't check right now (no access to a real machine).

I certainly do not mind an open-coded check though - we've done this for the 
VSX code too.

Alex

> 
> Thomas
>