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[Qemu-devel] [PATCH v5 02/37] target-arm: Implement AArch64 DAIF system
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v5 02/37] target-arm: Implement AArch64 DAIF system register |
Date: |
Fri, 28 Mar 2014 16:09:49 +0000 |
Implement the DAIF system register which is a view of the
DAIF bits in PSTATE. To avoid needing a readfn, we widen
the daif field in CPUARMState to uint64_t.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/cpu.h | 2 +-
target-arm/helper.c | 20 ++++++++++++++++++++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 78d4fc5..695a1e2 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -160,7 +160,7 @@ typedef struct CPUARMState {
uint32_t GE; /* cpsr[19:16] */
uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
- uint32_t daif; /* exception masks, in the bits they are in in PSTATE */
+ uint64_t daif; /* exception masks, in the bits they are in in PSTATE */
/* System control coprocessor (cp15) */
struct {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e642b30..c8348da 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1691,6 +1691,20 @@ static void aa64_fpsr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
vfp_set_fpsr(env, value);
}
+static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo
*ri)
+{
+ if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
+ return CP_ACCESS_TRAP;
+ }
+ return CP_ACCESS_OK;
+}
+
+static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ env->daif = value & PSTATE_DAIF;
+}
+
static CPAccessResult aa64_cacheop_access(CPUARMState *env,
const ARMCPRegInfo *ri)
{
@@ -1737,6 +1751,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "NZCV", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
.access = PL0_RW, .type = ARM_CP_NZCV },
+ { .name = "DAIF", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
+ .type = ARM_CP_NO_MIGRATE,
+ .access = PL0_RW, .accessfn = aa64_daif_access,
+ .fieldoffset = offsetof(CPUARMState, daif),
+ .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
{ .name = "FPCR", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
.access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
--
1.9.0
- [Qemu-devel] [PATCH v5 33/37] target-arm: Implement Cortex-A57 implementation-defined system registers, (continued)
- [Qemu-devel] [PATCH v5 33/37] target-arm: Implement Cortex-A57 implementation-defined system registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 14/37] target-arm: Implement AArch64 views of fault status and data registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 11/37] target-arm: Don't mention PMU in debug feature register, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 13/37] target-arm: Use dedicated CPU state fields for ARM946 access bit registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 05/37] target-arm: Add support for generating exceptions with syndrome information, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 12/37] target-arm: A64: Implement DC ZVA, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 17/37] target-arm: Implement AArch64 SPSR_EL1, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 23/37] target-arm: Implement AArch64 views of AArch32 ID registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 21/37] target-arm: Add Cortex-A57 processor, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 02/37] target-arm: Implement AArch64 DAIF system register,
Peter Maydell <=
- [Qemu-devel] [PATCH v5 20/37] target-arm: Implement ARMv8 MVFR registers, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 09/37] target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 08/37] target-arm: A64: Add assertion that FP access was checked, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 06/37] target-arm: Provide syndrome information for MMU faults, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 19/37] target-arm: Implement AArch64 EL1 exception handling, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 36/37] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc, Peter Maydell, 2014/03/28
- [Qemu-devel] [PATCH v5 27/37] target-arm: Remove THUMB2EE feature from AArch64 'any' CPU, Peter Maydell, 2014/03/28