[Qemu-devel] [PATCH microblaze v1 1/1] net: xilinx_axienet.c: Add phy soft reset bit clearing

[Peter Crosthwaite]

From: Nathan Rossi <address@hidden>

Clear the BMCR Reset when writing to registers.

Signed-off-by: Nathan Rossi <address@hidden>
[ PC:
 * Trivial style fixes to commit message
]
Signed-off-by: Peter Crosthwaite <address@hidden>
---

 hw/net/xilinx_axienet.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 839d97c..0f485a0 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -142,6 +142,9 @@ tdk_write(struct PHY *phy, unsigned int req, unsigned int 
data)
             phy->regs[regnum] = data;
             break;
     }
+
+    /* Unconditionally clear regs[BMCR][BMCR_RESET] */
+    phy->regs[0] &= ~0x8000;
 }
 
 static void
-- 
1.9.1.1.gbb9f595