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[Qemu-devel] [PULL 11/51] target-arm: Don't mention PMU in debug feature
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 11/51] target-arm: Don't mention PMU in debug feature register |
Date: |
Thu, 17 Apr 2014 11:33:26 +0100 |
Suppress the ID_AA64DFR0_EL1 PMUVer field, even if the CPU specific
value claims that it exists. QEMU doesn't currently implement it,
and not advertising it prevents the guest from trying to use it
and getting UNDEFs on unimplemented registers.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
This is arguably a hack, but otherwise Linux tries to prod
half a dozen PMU sysregs.
---
target-arm/helper.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4b6c1b6..62f7fd3 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2036,7 +2036,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_aa64dfr0 },
+ /* We mask out the PMUVer field, beacuse we don't currently
+ * implement the PMU. Not advertising it prevents the guest
+ * from trying to use it and getting UNDEFs on registers we
+ * don't implement.
+ */
+ .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
--
1.9.1
- [Qemu-devel] [PULL 21/51] target-arm: Add Cortex-A57 processor, (continued)
- [Qemu-devel] [PULL 21/51] target-arm: Add Cortex-A57 processor, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 19/51] target-arm: Implement AArch64 EL1 exception handling, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 22/51] target-arm: Implement AArch64 views of AArch32 ID registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 17/51] target-arm: Implement AArch64 SPSR_EL1, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 15/51] target-arm: Add AArch64 ELR_EL1 register., Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 16/51] target-arm: Implement SP_EL0, SP_EL1, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 23/51] target-arm: Implement AArch64 view of CONTEXTIDR, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 13/51] target-arm: Use dedicated CPU state fields for ARM946 access bit registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 14/51] target-arm: Implement AArch64 views of fault status and data registers, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 09/51] target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 11/51] target-arm: Don't mention PMU in debug feature register,
Peter Maydell <=
- [Qemu-devel] [PULL 12/51] target-arm: A64: Implement DC ZVA, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 08/51] target-arm: A64: Add assertion that FP access was checked, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 06/51] target-arm: Provide syndrome information for MMU faults, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 10/51] target-arm: Add v8 mmu translation support, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 05/51] target-arm: Add support for generating exceptions with syndrome information, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 02/51] target-arm: Implement AArch64 DAIF system register, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 03/51] target-arm: Define exception record for AArch64 exceptions, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 07/51] target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set, Peter Maydell, 2014/04/17
- [Qemu-devel] [PULL 04/51] target-arm: Provide correct syndrome information for cpreg access traps, Peter Maydell, 2014/04/17
- Re: [Qemu-devel] [PULL 00/51] target-arm queue, Peter Maydell, 2014/04/17