[Qemu-devel] [V2 PATCH 32/37] target-ppc: Introduce DFP Convert to Fixed

[Tom Musta]

Add emulation of the PowerPC Decimal Floating Point Convert to Fixed
instructions dctfix[q][.].

Signed-off-by: Tom Musta <address@hidden>
---
 target-ppc/dfp_helper.c |   36 ++++++++++++++++++++++++++++++++++++
 target-ppc/helper.h     |    2 ++
 target-ppc/translate.c  |    4 ++++
 3 files changed, 42 insertions(+), 0 deletions(-)

diff --git a/target-ppc/dfp_helper.c b/target-ppc/dfp_helper.c
index 0a53b26..3bbf8c6 100644
--- a/target-ppc/dfp_helper.c
+++ b/target-ppc/dfp_helper.c
@@ -944,3 +944,39 @@ static void CFFIX_PPs(struct PPC_DFP *dfp)
 
 DFP_HELPER_CFFIX(dcffix, 64)
 DFP_HELPER_CFFIX(dcffixq, 128)
+
+#define DFP_HELPER_CTFIX(op, size)                                            \
+void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *b)                  \
+{                                                                             \
+    struct PPC_DFP dfp;                                                       \
+    dfp_prepare_decimal##size(&dfp, 0, b, env);                               \
+                                                                              \
+    if (unlikely(decNumberIsSpecial(&dfp.b))) {                               \
+        uint64_t invalid_flags = FP_VX | FP_VXCVI;                            \
+        if (decNumberIsInfinite(&dfp.b)) {                                    \
+            dfp.t64[0] = decNumberIsNegative(&dfp.b) ? INT64_MIN : INT64_MAX; \
+        } else { /* NaN */                                                    \
+            dfp.t64[0] = INT64_MIN;                                           \
+            if (decNumberIsSNaN(&dfp.b)) {                                    \
+                invalid_flags |= FP_VXSNAN;                                   \
+            }                                                                 \
+        }                                                                     \
+        dfp_set_FPSCR_flag(&dfp, invalid_flags, FP_VE);                       \
+    } else if (unlikely(decNumberIsZero(&dfp.b))) {                           \
+        dfp.t64[0] = 0;                                                       \
+    } else {                                                                  \
+        decNumberToIntegralExact(&dfp.b, &dfp.b, &dfp.context);               \
+        dfp.t64[0] = decNumberIntegralToInt64(&dfp.b, &dfp.context);          \
+        if (decContextTestStatus(&dfp.context, DEC_Invalid_operation)) {      \
+            dfp.t64[0] = decNumberIsNegative(&dfp.b) ? INT64_MIN : INT64_MAX; \
+            dfp_set_FPSCR_flag(&dfp, FP_VX | FP_VXCVI, FP_VE);                \
+        } else {                                                              \
+            dfp_check_for_XX(&dfp);                                           \
+        }                                                                     \
+    }                                                                         \
+                                                                              \
+    *t = dfp.t64[0];                                                          \
+}
+
+DFP_HELPER_CTFIX(dctfix, 64)
+DFP_HELPER_CTFIX(dctfixq, 128)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 0f64fb8..30ba9d9 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -654,4 +654,6 @@ DEF_HELPER_3(drsp, void, env, fprp, fprp)
 DEF_HELPER_3(drdpq, void, env, fprp, fprp)
 DEF_HELPER_3(dcffix, void, env, fprp, fprp)
 DEF_HELPER_3(dcffixq, void, env, fprp, fprp)
+DEF_HELPER_3(dctfix, void, env, fprp, fprp)
+DEF_HELPER_3(dctfixq, void, env, fprp, fprp)
 #include "exec/def-helper.h"
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 76682f6..3f2f649 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -8392,6 +8392,8 @@ GEN_DFP_T_B_Rc(drsp)
 GEN_DFP_T_B_Rc(drdpq)
 GEN_DFP_T_B_Rc(dcffix)
 GEN_DFP_T_B_Rc(dcffixq)
+GEN_DFP_T_B_Rc(dctfix)
+GEN_DFP_T_B_Rc(dctfixq)
 /***                           SPE extension                               ***/
 /* Register moves */
 
@@ -11355,6 +11357,8 @@ GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
+GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
+GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
 #undef GEN_SPE
 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
     GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, 
PPC_NONE)
-- 
1.7.1