[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 03/14] tcg: Mask shift quantities while folding
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 03/14] tcg: Mask shift quantities while folding |
Date: |
Tue, 22 Apr 2014 14:05:53 -0700 |
The TCG result would be undefined, but we can at least produce one
plausible result and avoid triggering the wrath of analysis tools.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/optimize.c | 35 ++++++++++++++++++++---------------
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 7777743..2fb708e 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -220,34 +220,34 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg
x, TCGArg y)
return x ^ y;
case INDEX_op_shl_i32:
- return (uint32_t)x << (uint32_t)y;
+ return (uint32_t)x << (y & 31);
case INDEX_op_shl_i64:
- return (uint64_t)x << (uint64_t)y;
+ return (uint64_t)x << (y & 63);
case INDEX_op_shr_i32:
- return (uint32_t)x >> (uint32_t)y;
+ return (uint32_t)x >> (y & 31);
case INDEX_op_shr_i64:
- return (uint64_t)x >> (uint64_t)y;
+ return (uint64_t)x >> (y & 63);
case INDEX_op_sar_i32:
- return (int32_t)x >> (int32_t)y;
+ return (int32_t)x >> (y & 31);
case INDEX_op_sar_i64:
- return (int64_t)x >> (int64_t)y;
+ return (int64_t)x >> (y & 63);
case INDEX_op_rotr_i32:
- return ror32(x, y);
+ return ror32(x, y & 31);
case INDEX_op_rotr_i64:
- return ror64(x, y);
+ return ror64(x, y & 63);
case INDEX_op_rotl_i32:
- return rol32(x, y);
+ return rol32(x, y & 31);
case INDEX_op_rotl_i64:
- return rol64(x, y);
+ return rol64(x, y & 63);
CASE_OP_32_64(not):
return ~x;
@@ -806,29 +806,34 @@ static TCGArg *tcg_constant_folding(TCGContext *s,
uint16_t *tcg_opc_ptr,
case INDEX_op_sar_i32:
if (temps[args[2]].state == TCG_TEMP_CONST) {
- mask = (int32_t)temps[args[1]].mask >> temps[args[2]].val;
+ tmp = temps[args[2]].val & 31;
+ mask = (int32_t)temps[args[1]].mask >> tmp;
}
break;
case INDEX_op_sar_i64:
if (temps[args[2]].state == TCG_TEMP_CONST) {
- mask = (int64_t)temps[args[1]].mask >> temps[args[2]].val;
+ tmp = temps[args[2]].val & 63;
+ mask = (int64_t)temps[args[1]].mask >> tmp;
}
break;
case INDEX_op_shr_i32:
if (temps[args[2]].state == TCG_TEMP_CONST) {
- mask = (uint32_t)temps[args[1]].mask >> temps[args[2]].val;
+ tmp = temps[args[2]].val & 31;
+ mask = (uint32_t)temps[args[1]].mask >> tmp;
}
break;
case INDEX_op_shr_i64:
if (temps[args[2]].state == TCG_TEMP_CONST) {
- mask = (uint64_t)temps[args[1]].mask >> temps[args[2]].val;
+ tmp = temps[args[2]].val & 63;
+ mask = (uint64_t)temps[args[1]].mask >> tmp;
}
break;
CASE_OP_32_64(shl):
if (temps[args[2]].state == TCG_TEMP_CONST) {
- mask = temps[args[1]].mask << temps[args[2]].val;
+ tmp = temps[args[2]].val & (TCG_TARGET_REG_BITS - 1);
+ mask = temps[args[1]].mask << tmp;
}
break;
--
1.9.0
- [Qemu-devel] [PULL 00/14] tcg generic queue, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 01/14] tcg: Fix warning (1 bit signed bitfield entry) and replace int by bool, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 02/14] tcg: Use "unspecified behavior" for shifts, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 03/14] tcg: Mask shift quantities while folding,
Richard Henderson <=
- [Qemu-devel] [PULL 04/14] tci: Mask shift counts to avoid undefined behavior, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 06/14] tcg: Add TCGType parameter to tcg_target_const_match, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 05/14] tcg: Fix out of range shift in deposit optimizations, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 07/14] tcg-aarch64: Remove w constraint, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 08/14] tcg-ppc64: Use the type parameter to tcg_target_const_match, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 09/14] tcg-sparc: Use the type parameter to tcg_target_const_match, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 10/14] tcg-s390: Remove W constraint, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 12/14] tcg: Use tcg_gen_mulu2_i32 in tcg_gen_muls2_i32, Richard Henderson, 2014/04/22
- [Qemu-devel] [PULL 11/14] tcg: Relax requirement for mulu2_i32 on 32-bit hosts, Richard Henderson, 2014/04/22