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[Qemu-devel] [PATCH v2 04/13] tcg-sparc: Support trunc_shr_i32
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 04/13] tcg-sparc: Support trunc_shr_i32 |
Date: |
Thu, 24 Apr 2014 13:01:46 -0700 |
Unlike a 64-bit shift op, allows the output to be in %l or %i registers
for sparcv8plus.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/sparc/tcg-target.c | 8 ++++++++
tcg/sparc/tcg-target.h | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index f1226ab..4287bbe 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -1482,6 +1482,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc, const TCGArg *args,
case INDEX_op_ext32u_i64:
tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRL);
break;
+ case INDEX_op_trunc_shr_i32:
+ if (args[2] == 0) {
+ tcg_out_mov(s, TCG_TYPE_I32, args[0], args[1]);
+ } else {
+ tcg_out_arithi(s, args[0], args[1], args[2], SHIFT_SRLX);
+ }
+ break;
case INDEX_op_brcond_i64:
tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1],
@@ -1593,6 +1600,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_ext32s_i64, { "r", "r" } },
{ INDEX_op_ext32u_i64, { "r", "r" } },
+ { INDEX_op_trunc_shr_i32, { "r", "r" } },
{ INDEX_op_brcond_i64, { "rZ", "rJ" } },
{ INDEX_op_setcond_i64, { "r", "rZ", "rJ" } },
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index f44739f..61fd6b8 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -117,7 +117,7 @@ typedef enum {
#define TCG_TARGET_HAS_mulsh_i32 0
#if TCG_TARGET_REG_BITS == 64
-#define TCG_TARGET_HAS_trunc_shr_i32 0
+#define TCG_TARGET_HAS_trunc_shr_i32 1
#define TCG_TARGET_HAS_div_i64 1
#define TCG_TARGET_HAS_rem_i64 0
#define TCG_TARGET_HAS_rot_i64 0
--
1.9.0
- [Qemu-devel] [PATCH v2 00/13] tcg/sparc v8plus code generation, Richard Henderson, 2014/04/24
- [Qemu-devel] [PATCH v2 11/13] tcg-sparc: Fixup function argument types, Richard Henderson, 2014/04/24
- [Qemu-devel] [PATCH v2 09/13] tcg-sparc: Don't handle mov/movi in tcg_out_op, Richard Henderson, 2014/04/24
- [Qemu-devel] [PATCH v2 12/13] tcg-sparc: Fix small 32-bit movi, Richard Henderson, 2014/04/24
- [Qemu-devel] [PATCH v2 04/13] tcg-sparc: Support trunc_shr_i32,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 13/13] tcg-sparc: Accept stores of zero, Richard Henderson, 2014/04/24
- [Qemu-devel] [PATCH v2 05/13] tcg-sparc: Use 64-bit registers with sparcv8plus, Richard Henderson, 2014/04/24
- [Qemu-devel] [PATCH v2 02/13] tcg: Add INDEX_op_trunc_shr_i32, Richard Henderson, 2014/04/24
- [Qemu-devel] [PATCH v2 10/13] tcg-sparc: Hoist common argument loads in tcg_out_op, Richard Henderson, 2014/04/24
- [Qemu-devel] [PATCH v2 01/13] tcg: Fix missed pointer size != TCG_TARGET_REG_BITS changes, Richard Henderson, 2014/04/24
- [Qemu-devel] [PATCH v2 03/13] tcg-sparc: Remove most uses of TCG_TARGET_REG_BITS, Richard Henderson, 2014/04/24
- [Qemu-devel] [PATCH v2 06/13] tcg-sparc: Use the RETURN instruction, Richard Henderson, 2014/04/24
- [Qemu-devel] [PATCH v2 07/13] tcg-sparc: Implement muls2_i32, Richard Henderson, 2014/04/24
- [Qemu-devel] [PATCH v2 08/13] tcg-sparc: Tidy check_fit_* tests, Richard Henderson, 2014/04/24