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[Qemu-devel] [PULL 02/10] armv7m_nvic: fix CPUID Base Register
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 02/10] armv7m_nvic: fix CPUID Base Register |
Date: |
Thu, 1 May 2014 15:54:59 +0100 |
From: Rabin Vincent <address@hidden>
cp15.c0_cpuid is never initialized for ARMv7-M; take the value directly
from cpu->midr instead.
Signed-off-by: Rabin Vincent <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/armv7m_nvic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 6066fa6..f5b0c3b 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -173,7 +173,7 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
return 10000;
case 0xd00: /* CPUID Base. */
cpu = ARM_CPU(current_cpu);
- return cpu->env.cp15.c0_cpuid;
+ return cpu->midr;
case 0xd04: /* Interrupt Control State. */
/* VECTACTIVE */
val = s->gic.running_irq[0];
--
1.9.2
- [Qemu-devel] [PULL 00/10] target-arm queue, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 08/10] hw/arm/virt: Create the GIC ourselves rather than (ab)using a15mpcore_priv, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 07/10] target-arm: Correct a comment refering to EL0, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 02/10] armv7m_nvic: fix CPUID Base Register,
Peter Maydell <=
- [Qemu-devel] [PULL 05/10] target-arm: A64: Handle blr lr, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 09/10] hw/arm/virt: Put GIC register banks on 64K boundaries, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 01/10] target-arm: Implement XScale cache lockdown operations as NOPs, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 06/10] target-arm: A64: Fix a typo when declaring TLBI ops, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 03/10] target-arm: implement WFE/YIELD as a yield for AArch64, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 04/10] target-arm: Make vbar_write 64bit friendly on 32bit hosts, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 10/10] hw/arm/virt: Add support for Cortex-A57, Peter Maydell, 2014/05/01
- Re: [Qemu-devel] [PULL 00/10] target-arm queue, Peter Maydell, 2014/05/02
- Re: [Qemu-devel] [PULL 00/10] target-arm queue, Richard W.M. Jones, 2014/05/04