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[Qemu-devel] [PATCH v1 08/22] target-arm: A64: Add ELR entries for EL2 a
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v1 08/22] target-arm: A64: Add ELR entries for EL2 and 3 |
Date: |
Tue, 6 May 2014 16:08:12 +1000 |
From: "Edgar E. Iglesias" <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/cpu.h | 2 +-
target-arm/machine.c | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 7bac416..fd8ce70 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -163,7 +163,7 @@ typedef struct CPUARMState {
uint64_t daif; /* exception masks, in the bits they are in in PSTATE */
#define ELR_EL_IDX(x) (x - 1)
- uint64_t elr_el[1]; /* AArch64 exception link regs */
+ uint64_t elr_el[3]; /* AArch64 exception link regs */
uint64_t sp_el[4]; /* AArch64 banked stack pointers */
/* System control coprocessor (cp15) */
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 6a87ef6..92ac621 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -222,9 +222,9 @@ static int cpu_post_load(void *opaque, int version_id)
const VMStateDescription vmstate_arm_cpu = {
.name = "cpu",
- .version_id = 18,
- .minimum_version_id = 18,
- .minimum_version_id_old = 18,
+ .version_id = 19,
+ .minimum_version_id = 19,
+ .minimum_version_id_old = 19,
.pre_save = cpu_pre_save,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
@@ -243,7 +243,7 @@ const VMStateDescription vmstate_arm_cpu = {
VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
- VMSTATE_UINT64(env.elr_el[ELR_EL_IDX(1)], ARMCPU),
+ VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 3),
VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
/* The length-check must come before the arrays to avoid
* incoming data possibly overflowing the array.
--
1.8.3.2
- [Qemu-devel] [PATCH v1 03/22] target-arm: Make esr_el1 an array, (continued)
[Qemu-devel] [PATCH v1 06/22] target-arm: Move get_mem_index to translate.h, Edgar E. Iglesias, 2014/05/06
[Qemu-devel] [PATCH v1 07/22] target-arm: A64: Add SP entries for EL2 and 3, Edgar E. Iglesias, 2014/05/06
[Qemu-devel] [PATCH v1 08/22] target-arm: A64: Add ELR entries for EL2 and 3,
Edgar E. Iglesias <=
[Qemu-devel] [PATCH v1 09/22] target-arm: Add SPSR entries for EL2/HYP and EL3/MON, Edgar E. Iglesias, 2014/05/06
[Qemu-devel] [PATCH v1 10/22] target-arm: A64: Introduce arm64_banked_spsr_index(), Edgar E. Iglesias, 2014/05/06
[Qemu-devel] [PATCH v1 11/22] target-arm: Add a feature flag for EL2, Edgar E. Iglesias, 2014/05/06
[Qemu-devel] [PATCH v1 12/22] target-arm: Add a feature flag for EL3, Edgar E. Iglesias, 2014/05/06