[Qemu-devel] [PATCH v2 03/23] target-arm: adjust TTBCR for Security Extension feature

[Fabian Aggeler]

From: Sergey Fedorov <address@hidden>

TTBCR has additional fields PD0 and PD1 when using Short-descriptor
translation table format on a CPU with Security Extension support.

Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
---
 target-arm/helper.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 7898f40..9c3269f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1388,6 +1388,11 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const 
ARMCPRegInfo *ri,
 
     if (arm_feature(env, ARM_FEATURE_LPAE) && (value & (1 << 31))) {
         value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
+    } else if (arm_feature(env, ARM_FEATURE_SECURITY_EXTENSIONS)) {
+        /* In an implementation that includes the Security Extensions
+         * TTBCR has additional fields PD0 [4] and PD1 [5].
+         */
+        value &= (1 << 5) | (1 << 4) | (1 << 2) | (1 << 1) | (1 << 0);
     } else {
         value &= 7;
     }
-- 
1.8.3.2