Re: [Qemu-devel] [PATCH v3 19/22] target-arm: A64: Register VBAR_EL2

[Peter Crosthwaite]

On Mon, May 19, 2014 at 7:23 PM, Edgar E. Iglesias
<address@hidden> wrote:
> From: "Edgar E. Iglesias" <address@hidden>
>
> Signed-off-by: Edgar E. Iglesias <address@hidden>
> ---
>  target-arm/cpu.h    |  2 +-
>  target-arm/helper.c | 20 ++++++++++++++++++++
>  2 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 7322e03..693ad0f 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -198,7 +198,7 @@ typedef struct CPUARMState {
>          uint32_t c9_pmuserenr; /* perf monitor user enable */
>          uint32_t c9_pminten; /* perf monitor interrupt enables */
>          uint64_t mair_el1;
> -        uint64_t vbar_el[2]; /* vector base address register */
> +        uint64_t vbar_el[3]; /* vector base address register */
>          uint32_t c13_fcse; /* FCSE PID.  */
>          uint64_t contextidr_el1; /* Context ID.  */
>          uint64_t tpidr_el0; /* User RW Thread register.  */
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 5a2073e..7ca63a8 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2077,6 +2077,15 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
>      REGINFO_SENTINEL
>  };
>
> +/* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
> +static const ARMCPRegInfo v8_no_el2_cp_reginfo[] = {

Should it be v8_el3_no_el2_cp_reginfo?

Otherwise,

Reviewed-by: Peter Crosthwaite <address@hidden>

> +    { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
> +      .access = PL2_RW,
> +      .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
> +    REGINFO_SENTINEL
> +};
> +
>  static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
>      { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
>        .type = ARM_CP_NO_MIGRATE,
> @@ -2087,6 +2096,11 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
>        .type = ARM_CP_NO_MIGRATE,
>        .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
>        .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) 
> },
> +    { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
> +      .access = PL2_RW, .writefn = vbar_write,
> +      .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
> +      .resetvalue = 0 },
>      REGINFO_SENTINEL
>  };
>
> @@ -2356,6 +2370,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>      }
>      if (arm_feature(env, ARM_FEATURE_EL2)) {
>          define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
> +    } else {
> +        /* If EL2 is missing but higher ELs are enabled, we need to
> +         * register the no_el2 reginfos.  */
> +        if (arm_feature(env, ARM_FEATURE_EL3)) {
> +            define_arm_cp_regs(cpu, v8_no_el2_cp_reginfo);
> +        }
>      }
>      if (arm_feature(env, ARM_FEATURE_EL3)) {
>          define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
> --
> 1.8.3.2
>
>