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Re: [Qemu-devel] [PATCH v2 01/23] target-arm: add new CPU feature for Se
Re: [Qemu-devel] [PATCH v2 01/23] target-arm: add new CPU feature for Security Extensions
Wed, 21 May 2014 20:33:29 +0400
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On 21.05.2014 20:14, Christopher Covington wrote:
> Hi Peter,
> On 05/21/2014 10:46 AM, Peter Maydell wrote:
>> On 13 May 2014 17:15, Fabian Aggeler <address@hidden> wrote:
>>> From: Svetlana Fedoseeva <address@hidden>
>>> Define Security Extensions CPU feature. Set that feature for relevant CPUs.
>> This is potentially tricky because it means that CPUs which we were
>> previously implementing without TZ now boot up with TZ and in
>> Secure mode; I think this is probably the right thing but we'll need
>> to check that we don't break guests which were really expecting
>> to run in NS.
>> (Also I'm not sure what the semantics of -kernel should be for
>> TZ-supporting CPUs -- boot the kernel in S or NS ?)
> While Linux works in secure mode, non-secure hypervisor mode is required for
> KVM to work in the guest.
> "[Entry] in HYP mode ... is the recommended boot method ...."
AFAIK, in real hardware this switch to non-secure state is actually done
by bootloader. Why don't implement this in Qemu bootloader stub so far?
Re: [Qemu-devel] [PATCH v2 01/23] target-arm: add new CPU feature for Security Extensions, Peter Maydell, 2014/05/21
[Qemu-devel] [PATCH v2 02/23] target-arm: move SCR into Security Extensions register list, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 09/23] target-arm: add non-secure Translation Block flag, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 10/23] target-arm: implement CPACR register logic, Fabian Aggeler, 2014/05/13