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Re: [Qemu-devel] [PATCH v2] target-arm: implement CPACR register logic f
Re: [Qemu-devel] [PATCH v2] target-arm: implement CPACR register logic for ARMv7
Fri, 23 May 2014 14:14:28 +0100
On 19 May 2014 21:56, Fabian Aggeler <address@hidden> wrote:
> In ARMv7 the CPACR register allows to control access rights to
> coprocessor 0-13 interfaces. Bits corresponding to unimplemented
> coprocessors should be RAZ/WI. Bits ASEDIS, D32DIS, TRCDIS are
> UNK/SBZP if VFP is not implemented and RAO/WI in some cases.
> Treating TRCDIS as RAZ/WI since we neither implement a trace
> macrocell nor a CP14 interface to the trace macrocell registers.
> Since CPACR bits for VFP/Neon access are honoured with the CPACR_FPEN
> bit in the TB flags, flushing the TLB is not necessary anymore.
> Signed-off-by: Fabian Aggeler <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
I'll add this into the target-arm.next tree.